We are looking for a Senior Silicon Design Verification Engineer to join the team.
#SCHIE #CSME #SCIPS
Responsibilities
The candidate for this position will be expected and able to complete the following responsibilities:
Own the pre-silicon verification strategy and execution for one or more security IP blocks and subsystems and their integration into the SoC, covering test planning, environment architecture, and signoff criteria from early design through tapeout and silicon bring-up.
Architect and extend SystemVerilog and UVM environments that host C-based stimulus, connecting embedded test code to the testbench so processor-driven and stimulus-driven scenarios run together.
Drive coverage signoff across functional, code, and power-aware coverage. Set goals, investigate and close gaps without unjustified exclusions, and apply constrained-random, formal, and gate-level techniques to find bugs and prove test plan completeness.
Act as verification lead and technical point of contact for customer and partner teams, owning milestone delivery at both the IP and SoC levels, keeping releases on schedule.
Develop C and C++ based test content, low-level drivers, and custom firmware at the subsystem and SoC levels, including self-checking tests that run on embedded processors.
Qualifications
Required Qualifications
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
Other Requirements
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Citizenship & Citizenship Verification: This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
Preferred Qualifications
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
Experience developing tests in C/C++, SystemVerilog, and UVM, with emphasis on C/C++ test content for subsystem and SoC verification.
Experience owning pre-silicon verification of IP, subsystems, or SoCs through the full cycle, including test planning, test development, failure debug, and coverage signoff.
In-depth knowledge of verification principles, testbench architecture, and stimulus generation, with a track record of debugging complex designs.
Experience with low-level and embedded software, including assembly, startup code, linker scripts, and Makefile-based build flows.
Familiarity with industry protocols such as AMBA (AXI/AHB/APB), JTAG, SPI, I2C/I3C, and USB.
Experience collaborating across architecture, design, firmware, and validation teams, with communication skills.
Understanding of silicon and/or computer architecture.
Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
- Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
- https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.
