As a Senior Quantum Design Verification Engineer in the Quantum 1st Party Hardware System-on-a-Chip (SoC) team, you will play a critical leadership role in advancing the development of Microsoft’s quantum System-on-a-Chip verification infrastructure. Your responsibilities will include defining pre-silicon Simulation, post-silicon Validation/Characterization plans for SoC/ intellectual property (IP), and coordinating and driving individuals, contingent staff and external vendors towards creating a high-quality design.
Throughout the program lifecycle, you will engage with cross-functional teams—including architecture, quantum, verification, analog, physical design and vendors —to ensure that the design meets specifications and is successfully implemented and verified. This role requires proficiency & technical expertise, excellent communication skills, and the ability to manage complex design challenges in a collaborative environment.
This is a unique opportunity to be at the forefront of quantum hardware innovation. You will collaborate with leading physicists, quantum theorists, quantum experimentalists, research engineers, systems engineers, technical program managers, supply chain experts, cloud architects, and external partners to accelerate the scale-up of topological qubits and quantum systems that unlock unprecedented scientific and business value. If you are energized by complex program management challenges, thrive in ambiguity, and have a passion for foundational technologies that redefine what’s possible, we invite you to join us and help shape the future of quantum computing.
Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.
Responsibilities
Own and create verification environments and tests for IP level and SoC level designs, validate designs in simulation with both pre and post layout Register Transfer Level (RTL) / netlists.
Setup Databases, flows for SoC/IP repositories, manage them. Setup Bug-Tracking systems, log/track/manage/close bugs/issues. Drive Milestone reviews, reports/status
Create testplans for pre-silicon simulation verification, including for both digital and analog components; and performing Analog Mixed Signal Simulation models.
Collaborate with Design for Test (DFT) team to test DFT features
Align verification methodologies with wider teams and drive continuous improvement to the Design Verification development processes for at scale execution.
Collaborate effectively with architects, analog mixed-signal designers, verification engineers, physical design and DFT teams and other front-end designers.
Other
Embody our culture and values.
Qualifications
Required/minimum qualifications
Doctorate in Physics, Engineering, or related field AND 1+ year(s) experience in industry or in a research and development environment, could include completion of a post doctoral research position
OR Master's Degree in Physics, Engineering, or related field AND 4+ years experience in industry or in a research and development environment
OR Bachelor's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment
OR equivalent experience.
Other Requirements
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings:
Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Citizenship & Citizenship Verification: This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations (ITAR) or Export Administration Regulations (EAR), the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status (e.g., under 8 U.S.C. § 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
Preferred qualifications
Degree (BSEE/MSEE/PhD) in Electrical Engineering or related field
6+ years of experience in design verification with a proven track record of full verification cycle on complex SoC IPs and/or systems.
In depth knowledge of verification principles, testbenches, stimulus generation
Substantial background in creating simulation environments, developing tests, and debugging designs
Solid understanding of chip and/or computer architecture
Solid understanding of Analog/Digital interface verification, including modeling of Analog components as required.
Scripting language such as Python, Ruby, or Perl
Experience writing tests in C and C++
Effective communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
Artificial Intelligence (AI)-assisted solutions into verification flows and reporting to improve productivity and quality.
Matlab Modeling
Familiarity with Analog Mixed-Signal modeling and simulations
Visual Studio Code
Silicon Characterization of Analog Mixed-Signal blocks and release to production
Automation of simulation and data analysis environments using scripting languages or tools such as MATLAB/Python.
Ability to leverage AI tools to drive innovation and efficiency (e.g., performance modeling and analysis, research gathering, day to day task automation).
Ability to work in an “AI-first” environment using modern AI tools to accelerate discovery through hardware development.
#Quantum #QuantumCareers #MDQCareers
Quantum Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
- Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
- https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.
