We are looking for a Senior Physical Design Verification Engineer to join the team to support our mission and culture. This key role will impact the organization by helping deliver cutting edge silicon.
#SCHIE #CSME
Responsibilities
Work closely with top level and block level Physical Design Engineers on analysis and fixes on LVS, DRC, ERC, Antenna, etc.
Drive full chip integration for physical design verification, signoff and Tape-outs on the leading-edge technology nodes.
Collaborating with clock, analog, integration team on definition, implementation, and verification of critical chip routing, power delivery, block integration and other aspects.
Work with 3pIP and 1pIP teams for efficient and timely SOC-IP handshake.
Work with CAD team, tool vendors, foundry and other external partners to develop and validate new tools, flows, runsets, etc.
Utilize scripting/AI skills to write and customize tool flows to maximize design efficiency and productivity.
Qualifications
Required Qualifications
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
Other Requirements
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
Preferred Qualifications
BS/MS in Electrical or Computer Engineering/Electrical Engineering
5+ years of experience in semiconductor chip design/SOC physical design.
Experience in Physical Verification EDA tools like Mentor Calibre and Synopsys ICV.
Debugging skills for DRC, LVS, ERC, Antenna, High Voltage DRC, ESD, etc.
Multiple SOC Tape-Out experience in the advanced foundry process nodes.
Understanding of full chip integration, floor planning, IO RDL and bump planning.
Experience and knowledge of physical design flow and industry standard PNR tool (Fusion Compiler/Innovus, ICC2, etc.)
Understanding of transistor/device basics.
Proficient in scripting languages such as Perl, TCL, Python.
Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
- Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
- https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.
