We are looking for a Senior Logic Design Engineer to join the team designing RTL for a high-performance PCIe Subsystem supporting Azure Cobalt.
#SCHIE #CSME
Responsibilities
The candidate for this position will be expected and able to complete the following responsibilities:
Build a PCIe subsystem composed of multiple IP
Collaborate with architecture and IP providers to ensure the subsystem meets SOC requirements.
Grow your micro-architectural knowledge of your own blocks as well as other blocks in the SoC.
Assess and then refine the implementation for area, power and performance.
Perform design quality checks such as Synthesis, Lint, CDC, RDC, Low Power Intent, Logic Equivalence.
Understand Dataflow and Clocking requirements and drive solutions for timing critical paths.
Automate tasks using scripting for efficiency.
Delight your customers who receive your deliverable by providing high-quality functional block on schedule and with professional integrity.
Collaborate with highly energetic cross functional team members with respect and with One Microsoft mentality to establish synergies.
Challenge the status quo with a growth mindset.
Qualifications
Required Qualifications
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
OR equivalent experience.
Other Requirements
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings:
Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
Preferred Qualifications
Experience with high speed PCIe designs and protocols
Experience with Industry standard interface protocols such as AXI, APB, etc.
Experience with ARM Fabric IPs
Experience with IPXACT
Understanding of Computer Architecture fundamentals
Ability to write scripts using Python, Tcl, Perl etc.
Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus
Proficiency with UPF (Low power intent).
Proficiency in clock crossing techniques
Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals.
Applied understanding of low power design principles.
Understanding design closure challenges with power and clock domain crossings.
Experience writing timing constraints, exceptions, and clock constraints; good understanding in SDC commands and TCL constraints
Organized and detail-oriented
Good verbal and written communication skills.
Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
- Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
- https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.
