As a Senior Hardware Engineer – FPGA & Platform Security on SPARC, you will help define and build the hardware root of trust that protects Azure’s fleet, from silicon and FPGA prototypes through firmware, BMC, and datacenter deployment. You will translate security architecture into clear requirements, prototype and validate features such as secure boot, attestation, and secure recovery, and partner with silicon, firmware, and industry teams, including open efforts such as Caliptra and OCP S.A.F.E. This opportunity will allow you to deepen your expertise in hardware-rooted security, influence open industry standards, and see your work ship at hyperscale. This role is based in Redmond, WA or Mountain View, CA and requires three days per week in the office.
Responsibilities
Define requirements, specifications, and interface definitions for server platform features, including trust and integrity capabilities such as secure boot, attestation, and firmware recovery.
Lead bring-up of new server, SoC, and FPGA-based platforms, from first power-on through firmware, BMC, and OS boot, and work with hardware and firmware partners to resolve issues quickly.
Set up, maintain, and evolve lab infrastructure, including racks, networking, power, debug tooling, and remote management access, so engineers can validate new platforms efficiently.
Prototype and integrate root-of-trust and HSM capabilities (for example, Caliptra) on FPGA and emulation platforms, and develop validation plans that cover normal, fault, and recovery scenarios.
Build diagnostics, telemetry, and automated recovery tools that help fleet hardware detect problems, report its health, and return to a known-good state with minimal manual intervention.
Debug complex system-level issues across silicon, FPGA, firmware, BMC, and software boundaries, and turn findings into improvements in design, tooling, and process.
Partner with silicon vendors, ODMs, and industry groups such as OCP to drive adoption of platform requirements, mentor other engineers, and create reusable procedures and documentation.
Qualifications
Required Qualifications
Master's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 3+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 5+ years technical engineering experience OR equivalent experience
Other Requirements
Ability to meet Microsoft, customer and/or government security screening requirements is required for this role. These requirements include, but are not limited to, the following specialized security screening:
Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.
Preferred qualifications
Bachelor’s Degree in Electrical Engineering, Computer Engineering, or related field AND 8+ years technical engineering experience OR Master’s Degree in Electrical Engineering, Computer Engineering, or related field AND 6+ years technical engineering experience OR Doctorate Degree in Electrical Engineering, Computer Engineering, or related field AND 3+ years technical engineering experience OR equivalent experience.
Experience with hardware or platform security technologies such as secure boot, attestation, hardware root of trust, or cryptographic hardware.
Hands-on experience with FPGA design, prototyping, or emulation (Verilog/SystemVerilog and vendor toolchains) and lab bring-up of server or SoC platforms.
Experience with root-of-trust or HSM architectures (for example, Caliptra, TPM, DICE, SPDM) and platform firmware resiliency standards such as NIST SP 800-193.
Experience with server management and platform firmware (BMC, UEFI, PCIe/CXL), scripting in Python or C for automation, and cross-company collaboration through bodies such as OCP, TCG, or DMTF.
Hardware Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
- Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
- https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.
