Responsibilities
Own the end-to-end formal equivalency CAD flow, including RTL-to-netlist, netlist-to-netlist, functional ECO, and low-power (UPF-aware) verification, for Microsoft’s silicon programs
Develop, debug, and maintain production flows and automation in Tcl and Python for Synopsys Formality and Cadence Conformal, including handling of complex design classes
Partner with physical design, front-end/synthesis, and signoff teams and with EDA vendors (Synopsys, Cadence) to qualify new tool releases, resolve critical tool issues, and support design teams through tapeout closure
Independently drive technical decisions for the equivalency domain, identify root causes of ambiguous tool behavior, and define clear paths to resolution; mentor and serve as a backup for other engineers in the team
Deliver measurable improvements in flow quality, runtime, and reliability, including regression coverage, documentation, and support turnaround for design teams
Qualifications
Required Qualifications
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
Other Requirements
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings:
Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
Preferred Qualifications
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
5+ years of experience in silicon CAD, physical design (logic synthesis), or design verification flows using tools such as Synopsys Fusion Compiler/Design Compiler and/or Cadence Genus/Innovus
3+ years of hands-on experience with formal equivalency checking tools (Synopsys Formality and/or Cadence Conformal) in advanced process nodes
Proficiency in scripting and automation using Tcl and Python for developing and debugging production CAD flows
Experience with ECO flows, including functional-metal ECO and low-power (UPF-aware) equivalency verification
Experience qualifying and deploying EDA tool releases and working with vendor application engineers to drive issue resolution; familiarity with both Synopsys and Cadence equivalency tools
Effective communication and collaboration skills, with the ability to work effectively with distributed design and CAD teams and translate complex tradeoffs into clear next steps
Experience supporting multiple concurrent tapeouts and familiarity with cloud-based EDA compute environments
#AHSI
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Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
- Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
- https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.
