We are looking for a Principal Silicon Design Engineer to work on leading edge custom IP development as part of the SCIPS (Semi-Custom and Central IP Silicon) team within CSME (Compute Silicon & Manufacturing Engineering), the team responsible for Azure Cobalt chips. The candidate should excel at collaborating with other engineers to solve complex technical challenges.
#SCHIE #CSME #SCIPS
Responsibilities
The candidate for this position will be expected and able to complete the following responsibilities:
Own and lead FPGA design environment efforts for rapid IP prototyping and design validation including root-cause analysis of complex system issues.
Own development of custom IP RTL from microarchitecture through RTL implementation, verification, and post-silicon validation.
Collaborate with architecture, SoC, firmware, verification, and physical design teams to deliver high-quality FPGA and IP solutions.
Develop high-performance, power-efficient RTL designs and drive PPA optimization across the design lifecycle.
Lead design signoff activities including CDC, RDC, LINT, and timing closure
Mentor engineers and champion design excellence through reviews, automation, and continuous methodology improvements.
Qualifications
Required Qualifications
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
Other Requirements
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
Preferred Qualifications
- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ year(s) technical engineering experience or internship experience OR
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 8+ years technical engineering experience or internship
6+ years experience in digital logic design in SystemVerilog/Verilog/VHDL
6+ years experience running synthesis/static check tools including RTL synthesis, lint, CDC, RDC, and/or LEC
Expertise in digital design, microarchitecture specification development, and FPGA implementation.
6+ years of FPGA and RTL design experience
Expertise in Verilog/System Verilog
Expertise with FPGA designs (plan, build, troubleshooting, and debug)
Ability to read and write Python code
Experience developing and optimizing high-speed CMOS designs, including power, performance, and area tradeoff analysis
Debugging, problem-solving, and cross-functional collaboration skills throughout the IP development lifecycle
Written and verbal communication skills, with the ability to work independently and collaborate effectively across teams
Experience with Xilinx FPGA boards and tooling
Experience with ChipWhisperer or other similar FPGA power analysis tools
Experience setting up infrastructure for test automation and results checking
Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.
- Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
- https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.
