Responsibilities
Own verification of one or more features of a custom block or subsystem integration
Define and implement efficient UVM (Universal Verification Methodology)-based verification environments and use them to verify digital designs that are deployed in Microsoft’s cloud data centers
Implement verification coverage metrics and leverage them to achieve 100% coverage
Build and promote modern verification workflows, including AI-assisted techniques that improve verification environment development, automation, debug efficiency, coverage analysis, and execution quality
Define verification plans, quality metrics, regression strategy and coverage goals aligned with project milestones
Collaborate closely with architecture, design, system engineering and software partners to identify risks early, resolve complex issues, and deliver high-quality silicon subsystems
Qualifications
Required Qualifications
Master's Degree in Electrical Engineering, Computer Engineering, or related field
OR Bachelor's Degree in Electrical Engineering, Computer Engineering, or related field AND some technical engineering experience
OR equivalent experience
Other Requirements
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings:
Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
Preferred Qualifications
Doctorate in Electrical Engineering, Computer Engineering, or related field
OR Master's Degree in Electrical Engineering, Computer Engineering, or related field AND some technical engineering experience
OR Bachelor's Degree in Electrical Engineering, Computer Engineering, or related field AND solid technical engineering experience
OR equivalent experience
Proficiency in SystemVerilog-based verification environments and methodologies such as UVM, assertions, constrained-random verification, and coverage-driven verification
Proven experience in verifying digital designs
Ability to precisely articulate end goals and trade-offs when faced with ill-defined engineering challenges
Experience applying AI-assisted techniques to improve silicon design or verification productivity, debug, coverage, automation, or workflow efficiency
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This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.