We are looking for a Design Verification Engineer to join our team.
#SCHIE #CSME #SCIPS
Responsibilities
The candidate for this position will be expected and able to complete the following responsibilities:
Plan the verification of complex design IP interacting with the architecture and design engineers to identify verification test scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools
Develop tests using UVM or C/C++
Analyze and debug test failures with designers to deliver functionally correct design.
Identify and write functional coverage for stimulus and corner cases.
Close coverage to plug verification holes and meet tape-out requirements.
Collaborate with cross-functional teams, including Architecture, Design, Verification and FW to deliver products with key differentiators.
Engage in chip bring-up activities and write test firmware to assist other teams.
Drive innovation by enhancing validation efficiency through new methodologies and tools.
Embody Microsoft’s core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive Results, Influence for Impact, Judgement, and Diversity & Inclusion.
Qualifications
Required Qualifications
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience OR equivalent experience.
Other Requirements
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
Preferred Qualifications
3+ years of related technical engineering experience OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
Experience in executing pre-silicon verification of IPs/Sub Systems/SoCs through full cycle.
Background in creating and debugging IP/SoC Level tests in SV-UVM/C.
In depth knowledge of verification principles, testbenches and stimulus generation.
Solid understanding of silicon chip and/or computer architecture
Scripting language such as Python, Ruby or Perl.
Experience with the use of formal verification methods
Experience in Assembly, start up code and linker scripts
Experience in developing Makefiles for software development.
Silicon Engineering IC3 - The typical base pay range for this role across the U.S. is USD $102,100 - $202,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $133,800 - $219,200 per year.
- Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
- https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.
