Improve process capability, yield, cost efficiency, and wafer integrity through data‑driven optimization and equipment or consumable innovation.
Conduct root‑cause and failure‑mode analyses to understand wafer damage mechanisms such as edge chipping, micro‑cracks, subsurface damage, warpage, and residual stress, and drive mitigation strategies.
Perform fundamental research and early‑stage pathfinding to enable ultra‑thin wafer processing for next‑generation advanced packaging architectures.
Support process transfer and ramp to production at manufacturing sites; limited domestic and/or international travel may be required.
Minimum Qualifications
BS or MS degree with a minimum of 4 years of experience in wafer edge trim, backgrind, wafer thinning, CMP, or mechanical wafer processing in the semiconductor industry
Demonstrated research and development capability in science or engineering, with hands‑on experience advancing wafer processing capability through structured experimentation and learning.
Proven expertise in experimental design (DOE), data analysis, and result interpretation, translating findings into actionable process or technology improvements.
Strong analytical, physics‑based, and creative problem‑solving skills, applied to complex mechanical, material, and defect‑related wafer challenges.
Ability to apply deep understanding of wafer thinning, backgrind, and edge trim processes to influence technology direction, integration strategies, and long‑term roadmap decisions.
Proven success resolving complex process, yield, and reliability issues using root‑cause analysis, model‑based reasoning, and first‑principles understanding
Self‑motivated and capable of working independently with minimal supervision, while consistently delivering on technical and program commitments.
Demonstrated ability to manage numerous projects simultaneously, balancing near‑term execution with longer‑term R&D objectives.
Strong computer proficiency, including MS Office and data visualization tools, for effective reporting and executive‑level communication.
Preferred Qualifications
PHD in a related field with 2+ years of relevant industry experience
Proficiency in statistical analysis and statistical process control (SPC); experience applying statistics to variability reduction and process optimization
Exposure to or strong interest in advanced packaging technologies such as wafer‑level packaging, bonding/de-bonding, or 2.5D/3D integration is highly desirable
Familiarity with data science fundamentals, including Python scripting, automation, or GenAI‑enabled analysis
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
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To learn more about Micron, please visit micron.com/careers
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