Evaluate new DRAM/HBM architectural features and define validation requirements and testability needs before DBR.
Develop validation strategies for new and high-risk product features and promote reuse of validation methodology across product generations.
Leverage expert knowledge of DRAM and HBM architectures, including memory subsystem design, test infrastructure, protocol validation, timing characterization, and failure mechanisms, to define validation methodologies, identify risks early, and ensure robust product readiness.
Challenge design assumptions using silicon data, simulation results, and structured risk analysis.
Use Verilog/SystemVerilog simulation to identify validation gaps early and evaluate coverage and observability pre-silicon.
Minimum Qualifications
Bachelor’s or Master’s degree or equivalent experience in Electrical Engineering, Computer Engineering, or a related field, with 8+ years of semiconductor proven experience.
Proven expertise in both pre-silicon and post-silicon debug of DRAM/HBM issues.
Extensive experience analyzing schematics and performing timing-accurate (SPICE-level / transistor-level) simulations.
Experience with Verilog/SystemVerilog, Python, Linux environments, and version control systems (git, svn, Perforce).
Excellent problem-solving, analytical, communication, and technical presentation skills, with a track record of technical influence.
Preferred Qualifications
Experience defining validation strategy or coverage methodology for HBM or advanced DRAM products.
Experience influencing design-for-validation or testability decisions with Design Engineering or Design Validation teams.
Experience with validation hardware pathfinding, including probe cards, sockets, and interface boards.
Hands-on experience with lab equipment including oscilloscopes and logic analyzers, and with high-speed I/O and signal-integrity validation.
Experience defining or applying AI/ML or generative-AI solutions to validation, test, or debug workflows.
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