Dataline sensing: Design dataline sense amps and precharge/latch sensing, covering offset, Monte Carlo/high-sigma margin, coupling and IR drop.
Array repair & redundancy: Design column repair, fuse/repair storage and redundancy muxing with no bandwidth or timing penalty; verify all repair configurations with test, PE and FW.
AI-driven design: Use AI daily for RTL generation, scripting, and timing/waveform analysis; make specs and checklists AI-consumable and build agents that automate timing, Monte Carlo and repair-coverage checks.
Semi-custom methodology: Lead the move from SPICE-only closure to a semi-custom flow with characterized custom cells, SDC/STA sign-off, STA-to-SPICE correlation, and synthesis/APR/ECO flows.
Physical co-design: Drive floorplan, bus routing and RC-aware delay matching with layout, and correlate post-layout timing.
AI & technical leadership: Champion AI adoption and best practices, define interface specs with cross-functional teams, support silicon debug, and mentor engineers.
Minimum Qualifications
BS/MS in EE or related field with 8+ years in memory datapath, SRAM or high-speed custom design.
Deep expertise in flop-to-flop and wave-pipelined timing closure (setup/hold, skew, min/max delay, PVT margin).
Experience in sense amp, dataline or SRAM read/write design, including Monte Carlo/high-sigma verification.
Proven collaboration with layout on floorplanning, extraction and post-layout timing correlation.
Daily hands-on AI use, with concrete examples of AI-based workflows (prompts, scripts or agents) that improved productivity or design outcomes.
Preferred Qualifications
NAND/DRAM/SRAM periphery experience: page buffer, column decoder, global data bus, or array-to-IO pipeline.
Memory repair and redundancy design, and its impact on yield, area, timing and test time.
Timing-adjustment techniques (delay trims, DLL/DCC, training) and aging effects (NBTI/HCI).
Building AI agents, LLM/RAG pipelines or ML models for IC design, verification or debug.
Advanced CMOS device physics, mismatch modeling (BSIM), and low-power techniques (clock/power gating, leakage).
Working knowledge of STA and semi-custom flows mixing custom and standard-cell logic.
About Micron Technology, Inc.
We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.
To learn more, please visit micron.com/careers
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.
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