Dataline sensing: Design dataline sense amps and precharge/latch sensing, covering offset, Monte Carlo/high-sigma margin, coupling and IR drop.
Array repair & redundancy: Design column repair, fuse/repair storage and redundancy muxing with no bandwidth or timing penalty; verify all repair configurations with test, PE and FW.
Use AI daily for RTL generation, scripting, and timing/waveform analysis. Develop specs and checklists that AI can process. Build agents to automate timing, Monte Carlo, and repair-coverage checks.
Semi-custom methodology: Lead the move from SPICE-only closure to a semi-custom flow with characterized custom cells, SDC/STA sign-off, STA-to-SPICE correlation, and synthesis/APR/ECO flows.
Physical co-design: Drive floorplan, bus routing and RC-aware delay matching with layout, and correlate post-layout timing.
AI & technical leadership: Champion AI adoption and standard processes, define interface specs with multi-functional teams, support silicon debug, and mentor engineers.
Minimum Qualifications
BS/MS in EE or related field with 8+ years in memory datapath, SRAM or high-speed custom design.
Deep expertise in flop-to-flop and wave-pipelined timing closure (setup/hold, skew, min/max delay, PVT margin).
Experience in sense amp, dataline or SRAM read/write design, including Monte Carlo/high-sigma verification.
Proven collaboration with layout on floorplanning, extraction and post-layout timing correlation.
Daily hands-on AI use, with concrete examples of AI-based workflows (prompts, scripts or agents) that improved productivity or design outcomes.
Preferred Qualifications
NAND/DRAM/SRAM periphery experience: page buffer, column decoder, global data bus, or array-to-IO pipeline.
Memory repair and redundancy design, and its impact on yield, area, timing and test time.
Timing-adjustment techniques (delay trims, DLL/DCC, training) and aging effects (NBTI/HCI).
Building AI agents, LLM/RAG pipelines or ML models for IC design, verification or debug.
Sophisticated CMOS device physics, mismatch modeling (BSIM), and low-power techniques (clock/power gating, leakage).
Solid understanding of STA and semi-custom flows mixing custom and standard-cell logic.
The US base salary range that Micron Technology estimates it could pay for this full-time position is:
$181,000.00 - $308,000.00 a year
Additional compensation may include benefits, bonuses and equity. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
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