What You’ll Own
Digital Block Architecture & RTL Design
Own the micro-architecture and RTL implementation of all digital soft IP blocks — CSR/register file, clocking control logic, management bus interfaces, and control state machines — in synthesizable SystemVerilog.
Define and document block-level architecture specifications and interface control documents; serve as the authoritative reference for digital design intent.
Define CDC strategy for digital blocks and ensure clean closure using standard analysis tools.
Coordinate with the analog design lead on top-level chip integration, analog/digital partitioning, and chip boundary interface definitions.
Synthesis & Timing
Execute logic synthesis (Synopsys Design Compiler or Cadence Genus) and drive optimization toward PPA targets.
Develop and maintain block-level SDC constraints; execute and close static timing analysis (PrimeTime or Tempus) across required corners and modes.
Physical Design Interface
Serve as the primary digital interface to the layout and implementation team — providing synthesized netlists, SDC constraints, floorplan guidance, and design intent documentation to enable effective physical implementation.
Review and provide feedback on floorplan decisions, placement constraints, and timing closure results; partner with layout specialists to resolve implementation issues rooted in RTL or constraints.
Coordinate with the verification team on scan chain insertion, DFT strategy, and ATPG planning.
Where bandwidth and experience allow, participate directly in place-and-route and physical verification flows.
Self-Verification & Verification Support
Self-verify RTL through block-level simulation (VCS or Xcelium), waveform debug (Verdi or DVE), and directed testing before engaging the verification team.
Write SystemVerilog Assertions (SVA) for critical control sequences and protocol compliance.
Collaborate with the Design Verification Engineer on the block-level verification plan, testbench coverage, and bug resolution.
Support GLS and timing simulation using released netlists and SPF/parasitics; assist lab bring-up with simulation waveforms and register-level debug.
Documentation
Maintain block specifications, SDC rationale, implementation guidance, and ECO history as institutional knowledge for follow-on chip development.
What You Bring
Required
BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field
7–12 years of ASIC design experience with at least one complete front-to-back tape-out
Proficiency in synthesizable SystemVerilog RTL design — linting-clean, well-documented coding practices
Hands-on experience with logic synthesis (Design Compiler or Genus) and static timing analysis (PrimeTime or Tempus)
Proficiency with RTL simulation and debug tools (VCS or Xcelium; Verdi or DVE) for block-level self-verification
Solid understanding of CDC analysis methodologies (SpyGlass, JasperGold CDC, or equivalent)
Ability to work effectively at the interface between digital design and custom/analog implementation teams — translating design intent into actionable guidance for layout and implementation specialists
Strong written communication skills — this role produces specifications and documentation, not just code
Proficiency in leveraging AI tools for productivity across design, debug, and documentation workflows
Preferred
Experience working within a custom mixed-signal design team — comfortable operating alongside analog designers, layout engineers, and characterization specialists as a collaborative peer
Hands-on experience with place-and-route (Cadence Innovus or equivalent) and physical verification sign-off (Mentor Calibre) — candidates with full front-to-back implementation experience are strongly encouraged to apply
Experience with mixed-signal or PHY-adjacent chip implementation — analog/digital partitioning, analog supply isolation, mixed-signal physical integration
Familiarity with high-speed PHY architectures (SerDes, DDR, or equivalent)
Familiarity with digital infrastructure for observability and silicon characterization — including PRBS generators, error counters, monitor interfaces, debug registers, and support for first silicon bring-up
Familiarity with I2C management bus, Eye Monitor control logic, or PRBS-based error counting
Familiarity with DFT methodologies — scan insertion, ATPG planning, boundary scan
Experience with GLS flows using Liberty models and SPF parasitics
Familiarity with formal property verification (JasperGold or VC Formal)
Prior experience in a small team or startup-like environment
Why This Role
Deep digital ownership — from RTL architecture through synthesis, timing, and handoff to implementation — on a scope where your decisions are visible and your contributions immediately felt.
You will work alongside world-class engineers — a team of genuine collaborators.
The lean, senior team structure means your judgment is trusted and this is an individual contributor role with real impact.
Strong execution here creates a clear path to expanded scope and follow-on programs of increasing complexity.
A Note to All Candidates
We are building a long-term, high-caliber team around a compelling PHY technology program — and looking for engineers who want to own something, build something, and grow with a program. If that description resonates, we’d like to hear from you.
The US base salary range that Micron Technology estimates it could pay for this full-time position is:
$186,000.00 - $407,000.00 a year
Additional compensation may include benefits, bonuses and equity. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
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To learn more about Micron, please visit micron.com/careers
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