Partner closely with design teams to standardize, align, and continuously improve verification methodologies across projects and memory generations.
Develop, maintain, and evolve Python-based analog and reliability verification test benches, tools, and flows to support robust and scalable verification execution.
Provide technical leadership in verification methodology by setting priorities, mentoring engineers, and driving innovation for future DRAM technologies.
Leverage and apply AI to improve efficiencies and overall impact of work.
Minimum Qualifications
Bachelor’s or Master’s degree (preferred) in Electrical Engineering, Computer Engineering, or a related field.
10+ years of relevant experience in design and verification engineering.
Hands-on experience with gate-level analog simulation and debug environments (e.g., circuit simulation and waveform analysis).
Strong knowledge of VLSI circuit design fundamentals.
Advanced proficiency in Python programming, including object‑oriented design and use of advanced libraries.
Focused experience and proficiency in work with LLMs and Agentic AI tools
Preferred Qualifications
Strong understanding of DRAM circuit design and system architecture.
Knowledge of reliability fundamentals, including common degradation and failure mechanisms (e.g. BTI, HCI, EM, and TDDB) is a plus.
Excellent communication and collaboration skills, with the ability to influence across cross‑functional teams.
Self‑motivated, proactive team player who thrives in a diverse, collaborative environment.
Proven ability to manage multiple priorities with strong organizational and execution skills.
Demonstrated experience leading technical projects or initiatives.
Strong analytical and problem‑solving capabilities.
Passion for driving AI‑enabled process improvements and automation.
Expert‑level Python proficiency, with proven ability to design and implement multi‑layered, multithreaded, object‑oriented systems. Familiarity with digital verification methodologies (e.g., SystemVerilog, UVM).
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