Review and sign off on analog layouts
Drive layout‑aware build optimizations for advanced nodes
Define guidelines for analog build, documentation, and reuse
Collaborate across analog, digital, system, packaging, and test teams
Minimum Qualifications
MS or PhD in Electrical Engineering or related field
~10–15+ years of experience in analog/mixed-signal IC build
Proven expertise in
High-speed interface design
Clocking circuits (PLL/DLL/CDR)
Power management circuits
Strong experience in
Analog IP integration at subsystem or SoC level
SPICE simulation, extraction, and modeling
Silicon bring-up and lab validation
Deep understanding of
Advanced CMOS processes
Noise, jitter, SI/PI, and cross-domain coupling effects
Preferred Qualifications
Deep knowledge of DRAM sub‑system architecture, specification, operation, or build.
Understanding of Physical Layout & Circuit Floor Planning
Excellent Problem‑Solving & Analytical Skills
LLM
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