8+ years of experience in DRAM/memory or advanced CMOS verification
Strong circuit analysis and debug skills at the transistor level — able to root-cause behavior, not only at the testbench level
Experience with simulation tools such as HSPICE, Finesim, Verilog, or SystemVerilog
Deep understanding of CMOS fundamentals and semiconductor design principles
Demonstrated leadership, problem-solving, and ability to collaborate across multiple functions
Preferred Qualifications
Advanced degree (Master’s or PhD) in Electrical Engineering or related field, with equivalent experience considered
Experience with UVM, mixed-signal verification, and advanced DRAM architectures (e.g., DDR5 or beyond)
Strong background in verification methodology development and coverage strategies
Experience mentoring engineers and leading technical initiatives across teams
Recognition as an authority in DRAM build or verification domains
Strong programming skills (Python preferred) with ability to apply AI-assisted tools (e.g., ClaudeCode) to improve EDA automation, data analysis, and build efficiency
Responsibilities
Lead DRAM design and/or verification innovation, driving technical strategy and execution.
Collaborate with global teams to develop and share best-known methods across product lines.
Drive circuit improvement, verification planning, coverage closure, and silicon debug.
Define and implement tools, methodologies, and automation to improve quality and efficiency.
Provide technical leadership in mixed-signal simulation, validation, and signoff strategy for DDR5 and beyond.
Mentor engineers and serve as a DRAM authority for senior leadership.
Minimum Qualifications
Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field, or equivalent experience.
Strong expertise in DRAM design and/or verification for advanced memory products.
Hands-on experience with tools such as HSPICE, FINESIM, Verilog, and SystemVerilog.
Strong understanding of CMOS fundamentals, semiconductor design, and product development flows.
Demonstrated leadership, problem-solving, and multi-functional communication skills.
Preferred Qualifications
Advanced degree in Electrical Engineering or related field, or equivalent experience.
Experience with UVM, mixed-signal verification, advanced DRAM architectures, and DDR5+ methodology development.
Background in verification planning, coverage strategy, debug, and silicon correlation.
Experience mentoring engineers and leading technical initiatives across global teams.
Recognized authority in DRAM build, verification, or methodology development.
Strong programming skills (Python preferred) and ability to use AI-assisted tools (e.g., ClaudeCode) to improve EDA automation and productivity.
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