In this role, you will be a member of the MTIA (Meta Training & Inference Accelerator) Software team and part of the bigger AI and Compute Foundations team. The Graph Compiler team drives the development of the top-of-stack compilation pipeline for MTIA — taking PyTorch models, tracing the model graph, lowering and optimizing through FX/Inductor, and mapping to high-performance kernels. Your specific focus will be on performance optimization within the graph compiler: designing and implementing compiler passes that maximize throughput and minimize latency for AI workloads on MTIA hardware.
You will work closely with AI researchers to understand emerging model architectures and translate performance requirements into compiler optimization strategies. You will partner with hardware design teams to drive hardware-software co-design, ensuring the compiler exploits new silicon capabilities from day one. You will also collaborate with the Triton/DSL and LLVM compiler teams to deliver cross-stack performance improvements.
