Meta is looking for an experienced ASIC Package Engineer to join its ASIC Packaging team. This role owns the technology development and qualification readiness of the package-to-board attach process for Meta's custom AI/ML and networking silicon — the critical interface where a larger than reticle sized, large-body advanced package meets the motherboard Meta designs. The engineer will lead the development and optimization of package interaction with board attach processes. The Meta Infrastructure team designs, builds, brings up, tests, and integrates custom and general-purpose silicon-based hardware systems that power Meta's platforms, deployed in data centers worldwide. Designs are published through the Open Compute Project Foundation. We are building a deep competency in packaging technology to support the rapid development of custom silicon and to develop scalable packaging solutions that are optimal for our next-generation AI/ML products and system-level performance. As die sizes grow past 3.3x reticle and packages move to lidless/lidded and asymmetric stackups, board technology development for next gen ASIC is very important to achieve desired yield due to challenges with package warpage, thermo-mechanical stresses, and solder-joint reliability. The person in this role serves as the primary packaging expert for package to board technology development, working shoulder-to-shoulder with Product Quality Engineering (PQE), Supplier Quality Engineering (SQE), and module design teams to turn it into a fully qualified, statistically controlled, high-yield manufacturing process.
