What You Can Expect
Implement scan, compression, OCC, wrappers and MBIST on assigned blocks/partitions.
Run ATPG, analyze coverage, and drive coverage improvement (test points, fault exclusions).
Run DFT DRC, gate-level (zero-delay and SDF) simulations, and debug failures.
Support DFT timing constraints and closure with PD/STA teams.
Generate patterns and support silicon bring-up and ATE pattern debug.
Write scripts for flow automation; document methodology.
What We're Looking For
BS/MS in EE/CE; 5+ years of DFT experience, MS in EE/CE: 3+ years of experience
Hands-on with scan/ATPG/MBIST/JTAG using Synopsys or Siemens tools.
Good Verilog/SystemVerilog and scripting (Tcl/Python/Perl) skills.
Understanding of ASIC flow, STA, and gate-level simulation.
Good communication; works well in cross-functional teams.
- Expected Base Pay Range (USD)
- 113,920 - 170,600, $ per annum
The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.
 Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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