Proven experience on gate level simulations with notiming and SDF based simulations for DTT modes
Proven experience on Test structures for DFT, IP Integration, ATPG Fault models, test point insertion, coverage improvement techniques
Proven experience in Scan insertion techniques at block level and Chip top level
Good knowledge on Test mode timing constraints
Cross domain knowledge to resolve DFT issues with design, synthesis, Physical design, STA team
Proficiency in Industry standard Tools for Scan insertion, ATPG, MBIST and JTAG. (Preferably Synopsys/Mentor tools)
Good Knowledge and understanding on JTAG for IEEE1149.1/6 standards
Experience with Post-Si ramp up and debug on ATE
Good hands on experience on Memory BIST generation, Insertion, verification on RTL/Netlist level
Good knowledge on Perl/ Tcl scripting skills.
Very good team player capabilities and excellent communication skills to work with a variety of teams across the global organization
High sense of responsibility and ownership within the team for successful Tapeout and Post -Si ramp up of the project
What We're Looking For
Bachelor's degree in Computer Science, Electrical Engineering or related fields and 6 years of related professional experience in DFT.
- Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 4 years of experience.
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This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.

- Additional Compensation and Benefit Elements
With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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