Lead the Development of ATE Test Solutions, Silicon Bring-up and Characterization on new Tape-Outs, including Bench Validation, Correlation to simulation, Debug of First-Silicon Issues, Driving Cutting‑Edge Test Capability and ensuring Products meet the Highest Quality Standards
Design and Develop High‑Speed ATE Hardware Supporting Data Rates above 112 Gbps, Advancing Next‑Generation Test Methodologies and enabling Future‑Ready Semiconductor Products
Create Comprehensive Test Plans and Methodologies aligned with Stringent Product Specifications, ensuring Robust Validation and Consistent Product Performance
Collaborate closely with DFT, DFM and Design teams to Review Testability and Test Strategies, Contributing to Improved Yield, Optimized Test Methodologies, and Cross‑Functional Innovation
Convert Design‑level Test Content into ATE‑Ready Test Patterns, ensuring Seamless Transition from Simulation to Production Environments
Drive Test Flow Optimization, Reducing Test Time, Eliminating Redundant Steps, Improving Yields, and Releasing
High‑Quality Production Test Programs in Partnership with Cross‑Functional Engineering Teams
Manage Cost-of-Test Initiatives across the Product Lifecycle
Partner with Product Engineering, OSAT/foundry Test Floors on Test Program Transfer, Correlation, and Production Ramp Support
Represent Test Engineering in Design Reviews, Providing Testability, Test Coverage, and Cost-of-Test input early in the Design Cycle
Support Customer-Returns Technical Engagements (RMA), including Debug of Customer-Reported Silicon Issues and Test Escape Investigations
What We're Looking For
Bachelor’s degree in Electrical Engineering, Computer Engineering, or any related discipline
5 to 10 years of experience in Semiconductor Test Engineering, with Demonstrated Technical Leadership on Complex SoC/ASIC/analog Test Programs
Strong Hands-on Experience with Advantest 93000 ATE Platforms and SmarTest-8 Test Program Development
Deep understanding of DFT techniques: scan, BIST, boundary scan/JTAG, ATPG, SSN, and Test Coverage Analysis
Experience with Spanning New Product Introduction (NPI), Silicon Bring-up, Characterization, Correlation, and High‑Volume Manufacturing proven Technical Leadership in High‑Speed and High‑Power Semiconductor Test Development for AI, Networking, and Advanced Hyperscale Products
Deep expertise in ATE Test Methodologies, Silicon Process Fundamentals, DFT (Design-for-Test), DFM (Design-for- Manufacturing), High‑Speed SerDes, and High‑Power ATE testing.
Track record of Building Scalable and Reusable ATE Test Libraries and Test Methods for MCM, CPC, and CPO Product Lines
Proficiency in Scripting Test Automation, Data Analysis, and Computer Languages like Java, C/C++, Perl, and Python
Excellent Cross-Functional Communication Skills, with experience Presenting Yield/Quality Data to Senior Leadership and Customers
Demonstrates Strong Cross-Functional Communication Skills, with experience in Presenting Yield and Quality Data to Senior Leadership and Customers
Possesses effective Communication Abilities, Strong teamwork, and Problem Solving Skills
Self-motivated, Adaptable, and Capable of Thriving in Fast-Paced, Dynamic Engineering Environments
- Expected Base Pay Range (USD)
- 136,880 - 205,000, $ per annum
The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.
 Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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