Support electrical engineering activities including FPGA designs and system integration and testing with CAD and lab activities.
Analyze, design, and implement HDL test benches in hardware description languages, HDL (VHDL, Verilog), for code validation and validation against models.
Able to synthesize, place and route, meeting timing requirements from high-speed FPGAs.
Analyze, design, simulate, and implement designs which interface to common signaling standards, typical IP hard macros such as SERDES, PLLS, etc. and/or protocols such PCIe, 10GBE Ethernet, LVDS, etc.
Use judgment to perform technical troubleshooting and diagnosis of failed equipment and support root cause analysis.
Perform data analysis and write technical reports.
Develop and maintain design documents, functional requirements and interface control documents.
What You’ll Bring
BS and 5+ years of relevant experience as an electrical engineer or computer engineer in an R&D environment or Masters with 3+ year of relevant experience.
US Citizenship is required and must be able to obtain/maintain a Top Secret security clearance.
Experience or coursework related to testing FPGA or CPLD designs in an electronics lab.
Fluent in Vivado, Modelsim or Riviera. Fluent in testbenches and self-checking verification methods.
Working knowledge of electronics test equipment like function generators, oscilloscopes, logic analyzers, and lab power supplies.
Well-organized, reliable, attention to detail, demonstrated personal initiative. Ability to multi-task and prioritize workload. Good interpersonal skills and ability to coordinate work with others. Good oral and written communication skills.
Experience working with cross-functional R&D development teams.
Motivated self-starter able to work under minimal supervision and an entrepreneurial approach to roles and responsibilities.
Familiarity with GIT, JIRA, Agile, Scrum.
<20% travel to customer sites as required.
Even Better If You Have
Masters’ degree or higher in Electrical/Computer Engineering with emphasis on digital/ASIC/FPGA design is a plus.
Breadth of experience in a complementary discipline ability to develop image processing algorithms in Matlab and implement them in HDL, FPGA design, or embedded software is a plus.
Experience with Microchip Polarfire and Libero tools is a plus.
Experience reviewing and documenting technical data packages for military products.
Demonstrated mid-level lead position in a large FPGA project.
An active security clearance.
Why Leidos?
At Leidos, we deliver innovative solutions through the efforts of our diverse and talented people who are dedicated to our customers’ success. We empower our teams, contribute to our communities, and operate sustainably. Everything we do is built on a commitment to do the right thing for our customers, our people, and our community. Our Mission, Vision, and Values guide the way we do business.
Leidos Defense provides a diverse portfolio of systems, solutions, and services spanning land, sea, air, space, and cyberspace for customers worldwide. Our solutions include enterprise and mission IT, large-scale intelligence systems, command and control, geospatial and data analytics, cybersecurity, logistics, training, and intelligence analysis and operations support.
Our teams are solving some of the world’s toughest security challenges in support of customers with “can’t fail” missions.
Ready for your next engineering challenge? Bring your FPGA expertise to a team developing advanced technology in support of critical national defense missions.
If you're looking for comfort, keep scrolling. At Leidos, we outthink, outbuild, and outpace the status quo — because the mission demands it. We're not hiring followers. We're recruiting the ones who disrupt, provoke, and refuse to fail. Step 10 is ancient history. We're already at step 30 — and moving faster than anyone else dares.
Original Posting
August 17, 2026
For U.S. Positions: While subject to change based on business needs, Leidos reasonably anticipates that this job requisition will remain open for at least 3 days with an anticipated close date of no earlier than 3 days after the original posting date as listed above.
Pay Range
Pay Range $87,100.00 - $157,450.00
The Leidos pay range for this job level is a general guideline only and not a guarantee of compensation or salary. Additional factors considered in extending an offer include (but are not limited to) responsibilities of the job, education, experience, knowledge, skills, and abilities, as well as internal equity, alignment with market data, applicable bargaining agreement (if any), or other law.
