Key Responsibilities
Develop and maintain IP functional and behavioral models using Verilog, SystemVerilog, and, where applicable, SystemC and C++.
Translate IP specifications, schematics, RTL, and design intent into clear model requirements, implementation plans, and verification objectives.
Perform functional testing, audits, lint and CDC checks, regression testing, and consistency or equivalency checks against approved hardware references and specifications.
Lead or support the generation, audit, validation, and release of timing, power, signal-integrity, configuration, and metadata deliverables used for hardware and software integration.
Investigate and resolve model behavior, hardware-to-software integration, and customer-facing issues across the IP development lifecycle.
Develop scripts and reusable workflows that improve model generation, validation, audit, release, traceability, and reporting.
Partner with IP Design, Design Verification, Integration, Software, Architecture, and Applications teams to align requirements, ownership, quality expectations, and delivery schedules.
Lead technical reviews, provide sound engineering direction, mentor less-experienced engineers, and promote consistent modeling and verification practices.
Identify quality or process gaps and drive practical improvements that reduce manual effort, improve scalability, and shorten turnaround time.
Required Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
Demonstrated senior-level experience in digital, custom, analog, FPGA, ASIC, or IP modeling and verification environments.
Strong understanding of digital design fundamentals, RTL concepts, simulation, and the overall design and verification flow.
Proficiency in Verilog and/or SystemVerilog for functional or behavioral modeling and simulation.
Working knowledge of semiconductor and integrated-circuit principles, including the effects of device behavior, layout, timing, power, and signal integrity on system behavior.
Experience with digital simulation tools and familiarity with SPICE-type simulation, device models, or transistor-level design concepts.
Experience with scripting or programming languages such as Python, Perl, TCL, or Shell for engineering automation.
Ability to develop verification plans, define measurable completion criteria, analyze results, and drive technical issues to closure.
Strong collaboration and teamwork skills, with openness to working across multi-site and cross-functional teams
Good written and verbal communication skills, with the ability to ask clear questions, explain technical ideas, and learn from feedback
Preferred Qualifications
Experience developing models that represent custom digital or analog IP behavior.
Experience with timing, power, IBIS, signal-integrity, configuration, XML, or other metadata-based IP deliverables.
Experience with model equivalency, regression automation, lint, CDC, or structured design-quality audits.
Familiarity with FPGA development platforms and integrated hardware-software enablement flows.
Experience improving engineering processes, creating reusable methods, or deploying automation across multiple projects.
Experience mentoring engineers or providing technical leadership within a project team.
GenAI-Enabled Engineering Mindset
Uses approved GenAI tools responsibly to support learning, code review, debugging, documentation, automation, and technical summarization.
Proactively considers where GenAI can reduce repetitive work or improve quality, while independently verifying outputs and applying sound engineering judgment.
Protects confidential and proprietary information and follows applicable company policies when using AI-assisted tools.
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Additional Information
This position requires a successful background and reference checks and satisfactory proof of your right to work in: Philippines Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.
Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com. You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.
