Key Responsibilities
Develop stand-alone testbenches, directed and constrained-random tests, checkers, and scoreboards, in UVM or non-UVM format, to verify that functional and behavioral models match the actual hardware design.
Build regression suites, coverage collection, and coverage dashboards, and support release qualification of HLM, IP XML, and generated Chip Builder artifacts against measurable release-exit criteria.
Author, maintain, and execute test plans for assigned behavioral, functional, and architectural models, tracing each feature and behavior to tests and coverage points.
Execute formal equivalency runs using Conformal XL or other industry tools for assigned custom IPs, covering cell behavioralized model versus schematic, and custom IP functional model versus full IP schematic. Set up mappings and constraints and debug non-equivalent points to root cause.
Detect and triage RTL-model, schematic-model, primitive, XML, and configuration mismatches early in the development cycle, and work with model owners and design owners to drive them to closure.
Investigate and resolve model behavior, hardware-to-software integration, and customer-facing issues escaping into delivery, and feed lessons learned back into tests and coverage.
Develop scripts and reusable workflows that improve test generation, regression, audit, traceability, and reporting.
Report test status, coverage, equivalence results, and open issues in the team reporting cadence, and document assumptions and limitations.
Provide technical guidance, participate in technical reviews, and promote consistent verification practices across the Design Modeling team.
Required Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
Demonstrated senior-level experience (typically 5 or more years) in digital, custom, analog, FPGA, ASIC, or IP verification, validation, or modeling environments.
Strong understanding of digital design fundamentals, RTL concepts, simulation, and the overall design and verification flow.
Proficiency in Verilog and SystemVerilog, with working knowledge of UVM and stand-alone (non-UVM) testbench techniques.
Experience with digital simulation tools (such as Xcelium, VCS, or Questa) and familiarity with SPICE-type simulation, device models, or schematic and transistor-level design concepts.
Working knowledge of formal equivalence checking concepts and tools.
Experience with scripting or programming languages such as Python, Perl, TCL, or Shell for regression and flow automation.
Ability to develop test plans, define measurable completion criteria, analyze results, and drive technical issues to closure.
Strong collaboration and teamwork skills, with openness to working across multi-site and cross-functional teams.
Good written and verbal communication skills, with the ability to ask clear questions, explain technical ideas, and learn from feedback.
Additional Information
This position requires a successful background and reference checks and satisfactory proof of your right to work in: Philippines Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.
Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com. You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.
