Responsibilities
Digital Physical Design ASIC R&D engineer responsible for both module level as well as SoC Level implementation from RTL to GDS of digital and mixed signal ASICs. Solves complex and high impact design and development problems including customer application issues of varying scope and complexity. Uses product and customer applications knowledge to determine, define, develop, and validate design concepts and methods.
Participate in the entire spectrum of full ASIC design activities including definition, architectures, digital logic design, IP validation and synthesis.
Responsible for floor planning, place and route, timing closure, static timing analysis (STA), formal verification, low power design, clock distribution, EMIR analysis and physical verification
Close sign-off checks, interface with industry foundries and GDS delivery
Work extensively with cross functional teams to guide architecture with physical design constraints
Develop tool flows and drive vendors to achieve milestones
Qualifications
Bachelors or master’s degree in electrical or computer engineering. Typically, 0 - 2 years relevant experience.
Basic Qualifications
Desire to identify and debug problems.
Strong EE fundamentals with experience in ASIC Design, digital architectures/systems, digital circuit synthesis, and verification of large and mixed signal ASIC designs
Leadership skills to gain credibility and respect to drive change and influence teams and partners towards higher levels of execution, return, and productivity
Strong teamwork and written/verbal communication skills
Wanted Qualifications
Experience with Innovus and Tempus
Experience with task automation and scripting
Experience in digital and analog ASIC design flow, methodologies, and process
Experience with DFT architecture and implementation
Fluent with object-oriented programming
Ability to multi-task and to engage with multiple projects, engineers, and partnerships
Other Information
Relocation is available for this position
Visa Sponsorship is not available for this position
ITAR statement: This position requires access to certain goods, software, technology, or technical data subject to U.S. export control laws and regulations. Under these laws and regulations, U.S. persons (which includes U.S. citizens, U.S. nationals, lawful permanent residents, refugees, and asylees) working for Keysight can access export-controlled items without authorization from the U.S. government. For any individual who is not a U.S. person, Keysight may need authorization from the U.S. Department of State, U.S. Department of Commerce, or other appropriate federal agency before the individual can access export-controlled items. Employment in this position for non-U.S. persons is contingent on Keysight’s ability to obtain any required government authorizations.
We are unable to support visa sponsorship for this position.
Careers Privacy Statement
Keysight Technologies Inc. is an equal opportunity employer. Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, protected veteran status, disability or any other protected categories under all applicable laws.
Most offers will be between the minimum and the midpoint of the Salary Range listed below.
MIN $96,150.00 - MAX $160,250.00
Note: For other locations, pay ranges will vary by region
This role is eligible for Keysight Results Bonus Program
US Employees may be eligible for the following benefits
Medical, dental and vision
Health Savings Account
Health Care and Dependent Care Flexible Spending Accounts
Life, Accident, Disability insurance
Business Travel Accident and Business Travel Health
401(k) Plan
Flexible Time Off, Paid Holidays
Paid Family Leave
Discounts, Perks
Tuition Reimbursement
Adoption Assistance
ESPP (Employee Stock Purchase Plan)
Restricted Stock Units
#LI-MED1
About the Team
We are located in Colorado Springs, Colorado at the base of Pikes Peak. You’ll collaborate in a team environment to develop ASICs that meets customer functionality, schedule, and quality requirements. This job will be part of Keysight Laboratories, a world-renowned technology organization which enables Keysight to be first to market with breakthrough products and solutions.
Responsibilities
Digital Physical Design ASIC R&D engineer responsible for both module level as well as SoC Level implementation from RTL to GDS of digital and mixed signal ASICs. Solves complex and high impact design and development problems including customer application issues of varying scope and complexity. Uses product and customer applications knowledge to determine, define, develop, and validate design concepts and methods.
Participate in the entire spectrum of full ASIC design activities including definition, architectures, digital logic design, IP validation and synthesis.
Responsible for floor planning, place and route, timing closure, static timing analysis (STA), formal verification, low power design, clock distribution, EMIR analysis and physical verification
Close sign-off checks, interface with industry foundries and GDS delivery
Work extensively with cross functional teams to guide architecture with physical design constraints
Develop tool flows and drive vendors to achieve milestones
Bachelors or master’s degree in electrical or computer engineering. Typically, 0 - 2 years relevant experience.
Basic Qualifications
Desire to identify and debug problems.
Strong EE fundamentals with experience in ASIC Design, digital architectures/systems, digital circuit synthesis, and verification of large and mixed signal ASIC designs
Leadership skills to gain credibility and respect to drive change and influence teams and partners towards higher levels of execution, return, and productivity
Strong teamwork and written/verbal communication skills
Wanted Qualifications
Experience with Innovus and Tempus
Experience with task automation and scripting
Experience in digital and analog ASIC design flow, methodologies, and process
Experience with DFT architecture and implementation
Fluent with object-oriented programming
Ability to multi-task and to engage with multiple projects, engineers, and partnerships
Other Information
Relocation is available for this position
Visa Sponsorship is not available for this position
ITAR statement: This position requires access to certain goods, software, technology, or technical data subject to U.S. export control laws and regulations. Under these laws and regulations, U.S. persons (which includes U.S. citizens, U.S. nationals, lawful permanent residents, refugees, and asylees) working for Keysight can access export-controlled items without authorization from the U.S. government. For any individual who is not a U.S. person, Keysight may need authorization from the U.S. Department of State, U.S. Department of Commerce, or other appropriate federal agency before the individual can access export-controlled items. Employment in this position for non-U.S. persons is contingent on Keysight’s ability to obtain any required government authorizations.
We are unable to support visa sponsorship for this position.
Careers Privacy Statement
Keysight Technologies Inc. is an equal opportunity employer. Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, protected veteran status, disability or any other protected categories under all applicable laws.
Most offers will be between the minimum and the midpoint of the Salary Range listed below.
MIN $96,150.00 - MAX $160,250.00
Note: For other locations, pay ranges will vary by region
This role is eligible for Keysight Results Bonus Program
US Employees may be eligible for the following benefits
Medical, dental and vision
Health Savings Account
Health Care and Dependent Care Flexible Spending Accounts
Life, Accident, Disability insurance
Business Travel Accident and Business Travel Health
401(k) Plan
Flexible Time Off, Paid Holidays
Paid Family Leave
Discounts, Perks
Tuition Reimbursement
Adoption Assistance
ESPP (Employee Stock Purchase Plan)
Restricted Stock Units
#LI-MED1
