Kepler Communications
From Kepler Communications's careers page
Status: listed on the employer's own careers page when we last checked (daily). Confirm on their site before applying.
At Kepler, you’ll have the opportunity to work with a dedicated team of engineers building the Kepler spacecraft.
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Our mission is to provide real-time on-orbit connectivity for critical missions, enabling a new era of data-driven intelligence and innovation. With 33 satellites launched to date, Kepler operates the first commercial optical data relay constellation, enabling real-time, continuous space communications while supporting advanced on-orbit compute and hosted payload capabilities.
We’re on the hunt for a top-tier FPGA Digital Design Engineer to develop the next generation of our satellites.
At Kepler, you’ll have the opportunity to work with a dedicated team of engineers building the Kepler spacecraft. You will be responsible for the design and implementation of FPGA code either with a focus on DSP algorithms to modulate and demodulate signals on board our software defined radio (SDR), or embedded systems interfacing with processors and peripherals. To be effective you will need to participate in all phases of FPGA design flow (Simulation, Synthesis, Place & Route, Timing Closure and Hardware Testing). A good understanding of the intricacies of FPGA development would make a candidate standout.
Develop custom IP for new features of the Kepler satellite digital payloads
Iterate on current DSP and interface designs to improve reliability
Work with IP core vendors to integrate new functionality into the Kepler designs
Work with lead engineers in developing the communications and network architecture of our future satellite constellation
5+ yr. working experience with FPGA/RTL design
Verilog, SystemVerilog, or VHDL with the willingness to learn or pivot to SystemVerilog
Xilinx FPGA(s). Specifically, Zynq and UltraScale
Solid understanding of timing principles, including clock domain crossing and timing closure
Strong scripting skills (e.g Python, Tcl, csh/bash, etc.)
Experience in coherent digital demodulation of waveforms such as BPSK, QPSK, QAM
Experience with memory mapped interfaces such as AXI, Wishbone, Avalon
Experience with high-speed transceivers for protocols such as JESD204B, PCIe, SATA
Experience with Linting tools, Questa Sim or Riviera-Pro
Knowledge of radio-frequency electronics design
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