Create, validate, and maintain timing constraints (SDC), clock definitions, false paths, and multi-cycle paths.
Collaborate with RTL, DFT, STA, and Physical Design teams to resolve QoR, timing, power, and convergence issues.
Perform quality checks including LEC, CDC, lint, and low-power verification.
Analyze and improve synthesis QoR through scripting and flow enhancements.
Support tapeout activities and drive continuous improvements in synthesis methodologies.
Required Qualifications
Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or related field.
Strong understanding of ASIC design flow from RTL to GDS.
Hands-on experience with RTL synthesis, timing closure, and constraint development.
Expertise in Synopsys Design Compiler/Fusion Compiler or Cadence Genus.
Strong timing analysis knowledge using PrimeTime.
Experience with low-power design methodologies and UPF-based flows.
Good understanding of clocking architecture, timing constraints, and timing signoff.
Proficiency in TCL and scripting languages such as Python or Perl.
Excellent debugging, problem-solving, and cross-functional collaboration skills.
Preferred Qualifications
Experience working on AI/ML accelerators, NPU, DSP, GPU, CPU, or other high-performance compute architectures.
Knowledge of advanced technology nodes (5nm, 4nm, 3nm and below).
Experience with physical-aware synthesis and hierarchical design methodologies.
Familiarity with LEC, CDC, lint, power analysis, and low-power verification flows.
Proven track record of successful SoC or IP tapeouts.
Experience
Senior Engineer: 3-5 years of relevant experience.
Lead Engineer: 5-8 years of relevant experience.
Staff Engineer: 8-12 years of relevant experience.
Sr Staff Engineer: 12-18 years of relevant experience.
Principal Engineer: 18+ years of relevant experience.
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