Use statistical and spatial analytics to identify signatures by line, tool, material, panel position, geometry, product, and time.
Establish clear supplier actions, owners, completion criteria, control limits, and verification plans.
Support DFM/DFY, qualification, ramp readiness, change control, and deployment of dashboards or automated analytics.
Capture reusable learning and communicate facts, hypotheses, decisions, and residual risks clearly.
Qualifications
- Minimum qualifications
- Masters degree with 4+years or PhD with 2+years in Engineering, Materials Science, Physics, Chemistry, Data Science, or a related technical discipline.
- 4+ years of experience in semiconductor manufacturing, advanced packaging, substrate technology, yield engineering, process engineering, or a closely related field.
- Hands-on experience in substrate, advanced packaging, or semiconductor yield engineering, including statistical analysis, defect reduction, process optimization, SPC, DFM/DFY, defect metrology, failure analysis, and HVM execution.
- Strong analytical and problem-solving skills with the ability to make data-driven decisions in complex environments.
- Experience working across multiple organizations and influencing stakeholders to achieve results.
- Demonstrated ability to independently manage complex technical issues, execute with urgency, and drive actions to closure.
- Experience developing or deploying yield monitoring systems, automated analytics, dashboards, image analytics, computer vision, AI/ML-based defect detection, or automated defect classification systems.
- Professional proficiency in Mandarin and English sufficient for technical work, subject to HR validation.
Preferred qualifications
- Experience working directly with substrate suppliers and external manufacturing partners.
- Demonstrated program leadership experience, including coordinating cross-functional technical teams and driving execution in high-visibility, high-impact environments.
- Experience with semi-additive processing, build-up films, micro vias, copper plating, lithography, lamination, embedded silicon, TSV, 2.5D/3D packaging, or heterogeneous integration.
- Prior experience supporting technology development, qualification, and manufacturing ramp of advanced semiconductor technologies.
- Experience with automated data pipelines, dashboards, image analytics, computer vision, AI/ML defect detection, or automated defect classification.
Job Type
Experienced Hire
Shift
Shift 1 (Taiwan)
Primary Location
Taiwan, Taipei
Additional Locations
Taiwan, Hsinchu
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
- Work Model for this Role
- This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
