Key Responsibilities
Formulate and execute rigorous Design of Experiments (DOE) to optimize and qualify next-generation probing technologies and contact architectures for wafer and die sort operations
Serve as the lead technical liaison for Foundry and OSAT customers, translating complex chiplet and package requirements into scalable sort interface specifications
Author industry-standard sort design rules and Interface Design Kits (IDKs) to streamline ecosystem integration for external fabless customers and design partners
Collaborate with customer design and DFT teams to architect test interface hardware, resolve technical gaps, and synchronize testability roadmaps
Partner with global Test Solution vendors and PCB suppliers to pioneer state-of-the-art probing capabilities
Direct supplier and pathfinding initiatives to align vendor roadmaps with internal efficiency and performance goals
Drive supplier accountability and manufacturing readiness to guarantee on-time hardware delivery for critical New Product Introductions (NPI)
As a Successful Candidate, You Will Bring
Collaborative mindset — you thrive working across cross-functional teams, customers, and global suppliers
Strong communicator — you can translate highly technical concepts into clear, actionable specifications for diverse audiences
Analytical thinker — you approach complex problems with curiosity, structure, and data-driven decision-making
Self-starter — you take initiative, drive projects forward, and hold yourself and others accountable
Customer-focused — you understand the importance of building trust and delivering value to external partners
Adaptable — you are comfortable navigating ambiguity and evolving priorities in a fast-paced, cutting-edge environment
Continuous learner — you stay current with emerging technologies and proactively seek opportunities to grow
If you are passionate about pushing the boundaries of advanced packaging and test technology, and you want to make a meaningful impact on products that power the world's most advanced computing systems, we want to hear from you.
Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
Bachelor’s degree in electrical engineering, Mechanical Engineering, Materials Science, or a related STEM field with 6+ years of industry experience OR Master's degree in the same fields with 4+ years of industry experience OR Ph.D. in the same fields with 2+ year of relevant post-graduate or industry experience
Relevant industry experience can be any of the following
Experience with wafer/die sort Technology, prober-tester cell integration, and qualification of advanced probe card technologies
Structure and execute DOEs to evaluate probing margins, yield, and process health
Direct experience in ATE test hardware/methodology, Sort/Class product development, or PCB/space transformer/substrate design rules and stackup architectures
Preferred Qualifications
6+ years of experience in
Advanced probing process characterization
Direct experience managing technical relationships with external probe card/substrate suppliers or providing test hardware application support to external foundry/OSAT customers
Knowledge of OSAT/Foundry test operations, multi-client test cell standards, customer design collateral/PDK enablement, or turnkey test delivery models
Experience qualifying probe technologies for fine-pitch micro-bumps, 2.5D/3D architectures (EMIB, EMIB-T, silicon bridges), or wafer-level chip-scale probing
Hands-on experience with commercial ATE platforms such as Advantest V93k or Teradyne Ultra-FLEX
Job Type
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location
US, Oregon, Hillsboro
Additional Locations
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $133,800.00-255,200.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
- Work Model for this Role
- This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
