3. Evaluate tradeoffs between latency, bandwidth, scalability, and coherence domain complexity.
Memory Subsystem Architecture
1. Architect system memory subsystems including
DDR / LPDDR interfaces.
Memory controllers and scheduling policies.
Bandwidth provisioning and scaling strategies.
2. Work with Performance architect in define memory access models for compute, network, and accelerator subsystems.
3. Ensure optimal balance between latency-sensitive control workloads and bandwidth-intensive datapath workloads.
IO Memory and Virtualization Architecture (SMMU/IOMMU)
1. Define architecture for SMMU/IOMMU supporting virtualization-heavy IPU workloads.
2. Architect features such as
Multi-tenant isolation and security boundaries.
Shared vs isolated memory models.
3. Ensure efficient interaction between host, IPU/DPU compute, and offload engines.
System-Level Integration (Compute Network Storage)
1. Architect integration between
Compute subsystem.
Network subsystem (packet processing pipelines).
Storage and accelerator subsystems.
2. Optimize data movement across subsystems to minimize copies, latency, and bandwidth overhead.
3. Drive system architecture decisions for balanced SoC performance.
Power, Efficiency, and Scaling Strategy
1. Define compute and memory strategies for power efficiency and DVFS scalability.
2. Architect mechanisms for
Memory bandwidth throttling / prioritization.
Per-subsystem scaling.
3. Optimize performance-per-watt at system level.
Multi-Generation Architecture Roadmap
1. Lead long-term roadmap for compute and memory evolution across IPU/DPU product generations.
2. Define scaling strategies for
Core count and frequency.
Memory bandwidth and capacity.
Cache scaling and topology.
3. Ensure backward compatibility and smooth migration across product lines.
Cross-Functional Leadership
1. Collaborate with teams across
Networking subsystem (NSS).
SoC fabric/interconnect.
Firmware, OS, and drivers.
Validation and performance modeling and testing.
2. Drive architecture alignment and resolve cross-domain tradeoff.
Behavioral traits that we are looking for: (soft skills that you would like to see in a candidate)
Architectural vision: Defines long-term strategy across system domains.
Influence without authority: Drives alignment across multiple teams and disciplines.
Systems thinking: Understands interactions across compute, memory, network, and software.
Decision-making under ambiguity: Makes sound tradeoffs with incomplete data.
Collaboration: Builds strong cross-functional relationships.
Customer-oriented mindset: Translates workload needs into architectural innovations.
Ownership and accountability: Drives initiatives end-to-end.
Continuous learning: Stays current with evolving compute and memory technologies.
Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life.
See Intel Benefits for more details.
Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
Batchelor's degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of Study.
You must have 10 + years of experience in the following
SoC / CPU / memory subsystem architecture.
CPU architecture and cache hierarchies.
Memory subsystems (DDR/HBM, controllers, QoS).
Coherent/Non-Coherent interconnect architectures.
Experience in system-level performance and PPA tradeoff analysis.
Drive architecture definition from concept to silicon.
Preferred Qualifications
Post Graduate degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of Study.
ARM and x86 compute and memory subsystem experience, including NUMA systems, cache coherency, or large scale platform architectures.
Experience with IPU / SmartNIC or accelerator centric SoCs, particularly in cloud and hyperscale environments.
Familiarity with PCIe, CXL, and memory semantics for high performance IO.
Track record of multi generation architectural ownership and mentoring other architects.
Join us in building a brighter future through technology innovation!
Job Type
Experienced Hire
Shift
Shift 1 (Ireland)
Primary Location
Ireland, Leixlip
Additional Locations
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
EU Salary
We offer a total compensation package that ranks among the best in the industry. Annual Salary Range for this job which could be performed in Ireland is: €75,200.00 - €139,700.00

The compensation range displayed in this posting reflects the minimum and maximum target compensation for this position. Within this range, individual pay is determined by job related skills, experience, and relevant education, training. As part of our total compensation approach, the final offer may include additional pay components and benefits. Your recruiting team will share the confirmed base salary along with any applicable total compensation elements upon employment offer delivery.
- Work Model for this Role
- This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
