Troubleshoot packaging designs and resolve issues related to materials and processes, providing innovative and cost-effective solutions.
Implement co-design strategies between silicon and board design teams to optimize product performance and cost.
Collaborate with EDA partners to advance package design tools and optimize design methods.
Core Competencies
Strong analytical, communication, and organizational skills.
Proven ability to manage multiple priorities and deadlines in a dynamic environment.
Qualifications
The Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
US Citizenship required.
Ability to obtain and maintain US Government TS/SCI Security Clearance with Polygraph.
Option 1: Bachelor's degree in electrical engineering, mechanical engineering, chemical engineering, materials science or in a STEM related role with 6+ years of experience.
Option 2: Master's degree in electrical engineering, mechanical engineering, chemical engineering, materials science or in a STEM related role with 4+ years of experience.
Option 3: Ph.D. in electrical engineering, mechanical engineering, chemical engineering, materials science or in a STEM related role with 2+ years of experience.
2+ years of hands-on experience in semiconductor fabrication, chip assembly, or packaging.
Experience in electromagnetic simulation tools such as Mentor, Cadence tools, SPICE, Ansys tools, or similar platforms.
Experience with Cadence Allegro platform tools (PCB Editor, Advanced Package Designer, APD/SiP, Concept HDL, Sigrity) and/or Mentor Xpedition platform tools (PCB Layout/XPD, Designer, Hyperlynx).
In-depth knowledge of assembly processes, test methodologies, and characterization techniques.
Preferred Qualifications
Active US Government TS/SCI Security Clearance with Polygraph.
10+ years of experience with profound knowledge in Package, PCB design, or IC digital design.
Experience in troubleshooting and optimizing packaging designs for cost and quality.
Strong analytical and problem-solving skills, including the ability to identify, isolate, and resolve complex design issues.
Experience in semiconductor fabrication and packaging processes.
Experience collaborating with multidisciplinary teams across various levels of abstraction.
Experience with technology trade-off decisions to ensure high-quality package outputs.
We look forward to welcoming innovative thinkers who are passionate about shaping the future of technology. Apply today to make an impact and join Intel's journey toward groundbreaking advancements.
Job Type
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location
US, Arizona, Phoenix
Additional Locations
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $164,470.00-311,890.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
- Work Model for this Role
- This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
