Key Responsibilities
Own verification planning and execution for key IP features across IP and subsystem integration points
Build scalable verification environments and targeted test plans with reusable test benches, checkers, VIPs, and behavioral models
Collaborate closely with architecture, design, and software teams from specification through bringup; contribute across role boundaries when needed to unblock progress and maintain execution quality
Drive ownership of multiple critical blocks and verification components; take full responsibility for functional signoffs and achievement of performance and power metrics
Lead IP delivery to multiple customers while ensuring technical excellence; balance competing requirements, schedules, and resources across teams
Drive convergence of simulation and formal verification into unified bug hunting and coverage closure strategies; evaluate and adopt emerging methodologies including ML-driven verification flows
Mentor and develop verification engineers; establish verification best practices and raise team-level execution quality
Comfortable using AI-assisted development tools as part of everyday workflow; track record of delivering reusable, configurable verification collateral
Qualifications
Minimum Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
10+ years of experience in functional design verification of ASIC, SOC or FPGA designs with expertise in System Verilog, OVM/UVM, and debugging tools.
Proficiency in creating IP test environments and/or using formal verification methods
Strong knowledge of digital design fundamentals and microarchitecture principles.
Preferred Qualifications
Master's or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field with relevant experience in design verification.
Experience with formal property verification, System Verilog Assertions, code and functional coverage implementation and analysis
Experience collaborating across teams to drive architectural improvements.
Use of AI tools would be an advantage. At a minimum, require someone that is passionate about performing Pre-Silicon DV harnessing the power of AI.
Experience with switching/routing and communications protocols such as Ethernet, and Cryptographic Protocols such IPSec, DTLS and MACSec.
Experience with AMBA protocols such as APB and AXI.
Experience with languages such as SystemC, Python, Perl, Shell scripting and how AI can be used to integrate these in verification flows.
We invite you to bring your leadership, expertise and enthusiasm to a team where your contributions will drive technological progress and create opportunities for impactful learning and growth.
Job Type
Experienced Hire
Shift
Shift 1 (Ireland)
Primary Location
Ireland, Leixlip
Additional Locations
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
EU Salary
We offer a total compensation package that ranks among the best in the industry. Annual Salary Range for this job which could be performed in Ireland is: €75,200.00 - €117,500.00

The compensation range displayed in this posting reflects the minimum and maximum target compensation for this position. Within this range, individual pay is determined by job related skills, experience, and relevant education, training. As part of our total compensation approach, the final offer may include additional pay components and benefits. Your recruiting team will share the confirmed base salary along with any applicable total compensation elements upon employment offer delivery.
- Work Model for this Role
- This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
