Participates in the definition of architecture and microarchitecture features of the block being designed.
Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Supports SoC customers to ensure high-quality integration of the GPU block.
Business Group
The Data Center Group (DCG) develops advanced technologies that power data-intensive workloads across industries. As part of DCG, the GPU Hardware IP (GHI) team designs and validates next-generation graphics engines. The group's mission focuses on innovation in visual computing and delivering high-performance solutions that propel Intel's leadership in graphics. Joining this team means shaping the future of GPU development and contributing to impactful technologies.
Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.
Minimum Qualifications
Bachelors Degree in Electrical Engineering, Computer Engineering, or related STEM degree and 4+ years of industry experience OR Masters in Electrical Engineering, Computer Engineering or related STEM degree and 3+ years of industry experience OR PhD in Electrical Engineering, Computer Engineering or related STEM degree and 1+ years of industry experience.
Your experience should be in following
Scan, ATPG or other DFT features.
SoC or IP DFT design, integration or verification.
EDA tools such as Siemens Tessent or other ATPG tools, Synopsis VCS and/or other simulation or debug tools.
Preferred Qualifications
Silicon enabling debug or test pattern development experience.
Design automation skills and proficiency in programming or scripting languages.
Structural design flows, including timing, routing, placement or clocking analysis.
High volume manufacturing requirements and test flows.
3D, media and display graphics pipelines.
SoC architecture.
Job Type
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location
US, California, Folsom
Additional Locations
US, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, Hillsboro
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-172,860.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
- Work Model for this Role
- This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
