This role requires a full-stack verification mindset. You will create application-driven workloads using high-level software APIs while also developing robust HDL-based verification environments that ensure correctness at the lowest levels of hardware implementation. Working closely with architecture, design, and software teams, you will help drive verification strategies that enable first-pass silicon success.
An openness to learning new technologies and methodologies, such as asynchronous design techniques and AI-driven verification automation, is essential.
Responsibilities
Mapping application-level requirements to unit- and system-level test plans.
Write Python-based directed and random tests for design partitions and chip-level.
Running regressions, debugging test failures, tracking coverage and working with designers to fix failures and improve coverage.
Maintaining assertions, scoreboards and any tools/flows that are developed.
Integrating VIPs and coordinating with IP teams to ensure protocol requirements are met.
Qualifications
Minimum qualifications
Bachelors and 5+ years OR Masters and 3+ years of silicon engineering experience.
3+ years of pre-silicon verification or post-silicon validation experience in SoC accelerators or custom ASIC designs.
3+ years of experience in UVM and constrained random verification methods.
2+ years of experience developing the entire verification stack from test planning to execution, e.g. covering test development, coverage tracking, emulation, and post-silicon.
1+ year of experience using AI tools for test generation, debugging and improving overall productivity.
Preferred qualifications
Experienced in neuromorphic computing or AI/ML accelerator design.
Experience with commercial Verification IPs for standard IO interfaces, PHYs, and protocols such as Ethernet, PCIE, MACsec/IPsec, RoCEv2, MIPI CSI-2, JESD204.
Experience with DFX, low power and UPF verification techniques.
Job Type
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location
US, Oregon, Hillsboro
Additional Locations
US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Texas, Austin
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
- Work Model for this Role
- This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
