Collaborate with design and verification engineers to define interface contracts, share VIP and assertions, and debug interactions across data paths, clock and power transitions, reset sequences, and debug and trace functions
Work with architecture, design, and tooling engineers to clarify specifications, evaluate tradeoffs, and contribute reviewed changes to models, RTL, and verification infrastructure
Develop configuration-driven regressions and AI-assisted workflows for coding, property development, and debug; validate generated work with independent checks and reproducible tests across supported configurations
Mentor engineers through code and testplan reviews, communicate remaining risks, and establish clear evidence for verification closure
What We're Looking For
You should demonstrate the following professional traits to be successful:
Demonstrated ownership of complex verification work through closure, including cross-block root-cause analysis and clear technical communication across engineering disciplines
A collaborative approach to working across architecture, design, and verification teams to define requirements, resolve ambiguity, and drive toward shared goals
A rigorous, evidence-driven mindset — one that questions assumptions, validates generated work independently, and communicates risk clearly rather than relying on surface-level indicators of completeness
Qualifications
Minimum Qualifications
BS/MS in Electrical Engineering, Computer Science, or related field with 10+ years of relevant experience in design verification; background in IP DV with significant experience in subsystem and SoC-level verification
The experience must include
Hands-on experience verifying high-performance interconnects and memory subsystems, with an understanding of coherent, non-coherent, and I/O-coherent operation, cache coherency, memory consistency, transaction ordering, virtual memory, I/O Memory management units (IOMMUs), and interrupt controllers; experience with MESI/MOESI-based coherency mechanisms and protocols such as AMBA CHI, CXL, or comparable architectures
SystemVerilog/UVM and assertion-based verification skills, with practical experience applying formal verification alongside simulation and understanding the limits of each method
Programming and debugging skills in SystemVerilog and Python or C/C++; ability to read RTL, build independent reference models and checkers, and develop maintainable test automation
Preferred Qualifications
Experience with configurable interconnect generators, generated testbenches, and verification across topology, parameter, and multi-die configurations
Experience with formal abstraction and proof decomposition, or emulation-based validation of system workloads
Experience verifying clocking, power management, reset, debug, trace, RAS, security isolation, or QoS interactions at subsystem level
Knowledge of cache hierarchies, home nodes, duplicate-tag structures, snoop filters, memory controllers, and how their interactions affect correctness and performance
Experience building and evaluating AI-assisted engineering workflows, including checks for incorrect generated code, properties, or specification interpretations
Job Type
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location
US, California, Santa Clara
Additional Locations
US, Arizona, Phoenix, US, California, Folsom, US, Oregon, Hillsboro, US, Texas, Austin
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $190,610.00-269,100.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
- Work Model for this Role
- This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
