Collaborates with architects, design, verification, and validation engineers during the execution of the project.
Delivers definition of new microarchitecture and finds mitigations for issues that arise during feature implementation to improve the overall design of CPU and overcome bottlenecks and constraints.
Participates in the debug and fixing of performance miscorrelation between RTL and\or silicon results against the performance model.
Candidate must have experience in designing high performance CPUs and should be an expert in at-least one or multiple domains across the CPU (Branch Prediction, Fetch/Decode, Rename/Allocation, Reservation Stations/Execution, Memory Subsystem or Prefetchers and its interactions with Uncore).
Experience in debugging microarchitecture and simulation issues.
Strong background in microarchitecture/RTL/logic development.
Proven ability to resolve complex problems, applying analytical and technical skills effectively.
Qualifications
Minimum Qualifications
The candidate must have a Master's Degree with at 10+ years of experience or a PhD (with dissertation within a general CPU performance domain) with 6+ years of experience working within a high performance, high frequency ARM or x86 CPU performance team.
Candidate must have at 8+ years of continuous work within cycle accurate C++ CPU performance simulators
Preferred Qualifications
Background in CPU microarchitecture and experience modeling features in a cycle accurate performance simulator.
Experience in microarchitecture exploration and identifying new features which provide IPC across the CPU.
Experience with CPU performance related activities from inception to real silicon (pathfinding, definition, correlation with RTL and Post-Si performance debug and tuning)
Experience with performance scenarios/use cases and KPI/workloads
Advanced skills with Object Oriented Programming (C++/STL) and scripting languages
Ability to write assembly and craft tests to evaluate and debug microarchitectural features
Ability to read/debug performance issues in RTL
Join Intel and become part of a team dedicated to transforming computing architecture for a smarter, faster, and more connected world.
Job Type
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location
US, Texas, Austin
Additional Locations
US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Oregon, Hillsboro
Business group
Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $190,610.00-361,480.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
- Work Model for this Role
- This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
