Lead performance analysis of real-world applications, AI/HPC workloads, and industry benchmarks; identify bottlenecks spanning the compiler, runtime, libraries, and microarchitecture; and drive the work that closes the gap.
Identify, design, and productize compiler optimizations and code generation that expose new Intel CPU and GPU capabilities, taking features from prototype through to shipping quality.
Own performance for a compiler component or workload domain - set the targets, track them through continuous integration, and be accountable for both regressions and gains.
Advance heterogeneous and offload compilation across SYCL, OpenMP, Triton, MLIR, and DSL paths, improving portability without sacrificing performance.
Collaborate closely with hardware architecture teams to influence how future Intel silicon is defined and exposed through the compiler and language stack.
Contribute to and collaborate with upstream open-source communities: drive designs through public RFCs, upstream patches, and review community contributions.
Influence technical direction and architecture, review designs and code, and raise engineering standards across the team.
Mentor and coach junior engineers, and represent the team's work to partners, customers, and the broader ecosystem.
As a senior engineer you will have significant opportunity for technical depth and for shaping the vision of future compilers and software tools.
Qualifications
Minimum Qualifications:
Master's or PhD in Computer Science, Computer Engineering, or a related field with 5+ years of relevant industry experience; or a Bachelor's degree with 8+ years.
Strong knowledge base and hands-on experience in modern C++, data structures and algorithms, and compiler theory.
Production experience in at least one area of the compiler stack: middle-end optimization, backend code generation, language front end, or runtime and offload support.
Demonstrated experience in performance analysis and tuning of real-world applications on CPU and/or GPU.
Proven track record of analyzing and solving complex technical problems and delivering features through a full product cycle.
Excellent written and oral communication skills, with the ability to clearly communicate technical details and concepts to engineers, architects, and stakeholders.
Preferred Qualifications
Substantial experience with LLVM compiler infrastructure, including upstream contributions; experience with MLIR is a strong plus.
Deep knowledge of Intel x86 instruction set architecture and Advanced Vector Extensions, or of GPU architecture and execution models.
Experience with heterogeneous and parallel programming models - SYCL, OpenMP offload, Triton, OpenCL, or CUDA.
Experience optimizing AI/ML workloads or integrating compiler technology with frameworks such as PyTorch and inference engines.
Experience with CI and performance-tracking infrastructure at scale.
Experience leading projects across geographies and mentoring engineers.
Job Type
Experienced Hire
Shift
Shift 1 (China)
Primary Location
PRC, Shanghai
Additional Locations
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
- Work Model for this Role
- This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
