Job Details
Job Description
We are seeking a highly motivated Senior CAD Engineer for CPU IP Design Planning Methodology and Automation to support, maintain, enhance, and deploy Design Planning and RTL to Floorplan methodologies for next generation CPU IP development.
The successful candidate will work closely with CPU Physical Design, Architecture, RTL, and CAD teams to enable efficient and scalable Design Planning workflows. This role focuses on methodology development, flow support, automation, infrastructure maintenance, and productivity improvements across multiple CPU programs.
The ideal candidate combines a strong understanding of Physical Design and Design Planning concepts with expertise in CAD methodologies, EDA tools, scripting, and software development.
Key Responsibilities
Own and support Design Planning and RTL to Floorplan methodology deployment across CPU IP programs.
Develop, maintain, and enhance automation frameworks supporting RTL to Floorplan, Design Planning, physical aware RTL analysis, floorplan generation flows, PPA estimation methodologies, and early congestion and routability analysis.
Provide technical support to Physical Design teams by debugging flow, tool, and methodology issues.
Drive continuous improvements in Design Planning flow quality, robustness, scalability, and usability.
Develop automation solutions to improve engineering productivity and reduce manual effort.
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Create dashboards, reporting infrastructure, and analytics frameworks to track methodology health, usage, and quality metrics.
Work closely with implementation teams to identify workflow bottlenecks and deploy automation based solutions.
Support the adoption and deployment of new EDA tool capabilities, releases, and methodology enhancements.
Enable methodology correlation and consistency across CPU IP projects and technology nodes.
Partner with internal CAD organizations and EDA vendors to evaluate and integrate new Design Planning capabilities.
Drive best practices, documentation, training materials, and user support for Design Planning methodologies.
Explore Machine Learning, Generative AI, and Agentic AI solutions to improve methodology deployment, flow debugging, and productivity.
Qualifications
- Minimum Qualifications
- M.Tech/MS in Electrical Engineering, Computer Engineering, Computer Science, VLSI, or a related field.
- 4+ years of industry experience in:
- CAD Engineering
- Design Automation
- Physical Design Methodology
- EDA Tool Development
- Physical Design Infrastructure
- Strong understanding of:
- Physical Design flows
- RTL-to-Floorplan methodologies
- Design Planning concepts
- Floorplanning fundamentals
- PPA analysis and optimization
- Experience supporting and deploying implementation tools such as:
- Synopsys Fusion Compiler
- ICC2
Preferred Qualifications
- Experience supporting CPU Core, Cache, Fabric, or other high-performance IP development teams.
- Experience developing methodologies and automation for:
- RTL-FP
- Design Planning
- Physical-aware design
- Design quality assessment
- Early PPA estimation
- Experience with advanced technology nodes such as Intel 18A/14A, TSMC N3/N2, or equivalent.
- Experience with distributed compute infrastructure, cloud-based design environments, and large-scale CAD systems.
- Familiarity with Machine Learning, Data Analytics, LLMs, and Agentic AI frameworks for EDA applications.
- Working knowledge of timing, power, congestion, routability, and signoff considerations impacting design planning methodologies.
Job Type
Experienced Hire
Shift
Shift 1 (India)
Primary Location
India, Bangalore
Additional Locations
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
- Work Model for this Role
- This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
