In this role, you will be responsible for
The architecture, design, implementation, and validation of high-speed analog and mixed-signal integrated circuits used in advanced optical interconnect products.
You will collaborate closely with cross-functional design teams to deliver innovative solutions from concept through production.
Define circuit architectures and develop designs that meet power, performance, and functionality requirements for next-generation optical interconnects.
Lead block-level design and collaborate with multidisciplinary teams to deliver key integrated circuit components.
Architect, design, and validate high-speed, low-voltage, low-power analog and mixed-signal integrated circuits.
Work closely with digital design teams to ensure successful integration and product execution.
Plan and execute design activities while balancing performance, schedule, and quality objectives.
Guide to the development of post-silicon test and characterization plans.
Create and maintain comprehensive design documentation, including design specifications, reviews, and technical reports.
Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.
Minimum Qualifications
M.S. degree in Electrical Engineering or a related field with 4+ years of industry experience or PhD & 2+ years in the following:
Hands-on experience designing high-speed circuit blocks such as amplifiers, drivers, equalizers, PLLs, phase interpolators, and clock and data recovery (CDR) circuits for data rates of 32 Gbps and above.
Experience designing inductors, transmission lines, transimpedance amplifiers (TIAs), and optical modulator drivers.
Strong expertise in high-speed serial link design and analog CMOS/BiCMOS circuit design using deep-submicron process technologies.
Experience with full-chip integration, ESD design considerations, and verification methodologies.
Preferred Qualifications
Familiarity with optical communication systems.
Experience developing 400G, 800G, and 1.6T optical links.
Experience with package design and test setup development.
Experience designing precision analog circuits such as ADCs and DACs.
Experience with PAM4 and NRZ link architectures.
Strong understanding of mixed-signal design methodologies and flows.
Excellent written and verbal communication skills.
Job Type
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location
US, California, Santa Clara
Additional Locations
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
- Work Model for this Role
- This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
