Key Responsibilities
Lead packaging integration research programs focused on heterogeneous integration, chiplets, 2.5D/3DIC, hybrid bonding, wafer-level packaging, and emerging die-to-die interconnect technologies.
Define integration research strategy, technical roadmaps, research milestones, and decision criteria aligned to future product, platform, and system-level scaling requirements.
Manage multidisciplinary team of integration researchers, packaging technologists, process integration engineers, modeling experts, design, and technical program leads.
Translate system requirements into package integration solutions by balancing performance, power, area, latency, bandwidth, thermal behavior, mechanical stress, reliability, cost, and manufacturability.
Partner with silicon design, device, process, substrate, assembly, test, reliability, thermal, signal integrity, power delivery, failure analysis, and manufacturing teams to close cross-domain integration gaps.
Drive feasibility studies, architecture trade-off analysis, process module evaluation, design rule development, prototyping, design-of-experiments, and experimental validation for new integration concepts.
Lead technology readiness assessments, integration risk reviews, failure analysis learning cycles, reliability evaluations, and manufacturing feasibility reviews for early-stage packaging options.
Drive intellectual property, technical publications, competitive benchmarking, and internal knowledge transfer related to advanced packaging integration.
Guide research-to-development transfer by defining integration requirements, qualification gaps, process control needs, manufacturability risks, cost implications, and scaling paths.
Communicate technical progress, trade-offs, risks, investment needs, and strategic recommendations to senior technical and business leaders.
Key Competencies
Si-Package co-optimization across process, integration, electrical, thermal, mechanical, reliability, manufacturability, and cost dimensions
Advanced packaging integration research leadership and technical vision
Heterogeneous integration, chiplet, 2.5D/3DIC, hybrid bonding, and emerging interconnect expertise
Technology pathfinding, roadmap definition, research portfolio management, and research-to-development transfer
Modeling, simulation, prototyping, experimentation, failure analysis, and data-driven integration learning
Cross-disciplinary influence across device, design, process, materials, test, reliability, thermal, electrical, and manufacturing teams
External ecosystem collaboration with universities, consortia, suppliers, and equipment vendors
Strategic communication, risk framing, and executive-level technical storytelling
Required Skills and Experience
Demonstrated experience leading advanced technology research programs, multidisciplinary technical teams, cross-functional initiatives, or external research collaborations.
Ability to convert ambiguous integration challenges into clear hypotheses, experimental plans, measurable milestones, technology readiness criteria, and actionable recommendations.
Strong understanding of package-system integration, chiplet architectures, advanced interconnects, substrates, interposers, assembly materials, wafer-level processes, thermal-mechanical behavior, power delivery, signal integrity, reliability, and manufacturability trade-offs.
Strong communication skills with the ability to present complex technical findings, integration trade-offs, risks, and recommendations to executive, technical, and cross-functional audiences.
Preferred Skills and Experience
Strong record of innovation in semiconductor packaging integration, heterogeneous integration, chiplet architectures, 2.5D/3DIC, hybrid bonding, interposer technology, fan-out, wafer-level packaging, substrate technology, or package-system co-optimization.
Experience with research-to-development transfer, technology readiness frameworks, pathfinding, prototype builds, process integration learning, and early manufacturing feasibility assessment.
Knowledge of thermal-mechanical modeling, warpage, stress, CTE mismatch, electromigration, reliability physics, high-speed I/O, power integrity, signal integrity, die-to-die interfaces, and package-level co-design.
Demonstrated record of patents, publications, conference presentations, industry consortia participation, university research collaboration, or external ecosystem leadership.
Experience leading multi-organization collaborations with suppliers, equipment vendors, universities, research labs, OSATs, foundry partners, design teams, or customer technology teams.
Familiarity with AI, HPC, data center, automotive, mobile, networking, edge computing, advanced memory, or custom silicon packaging requirements.
Qualifications
Master’s degree in electrical engineering, Mechanical Engineering, Materials Science, Chemical Engineering, Applied Physics, Microelectronics, Semiconductor Manufacturing, or a related engineering or science discipline. Ph.D. Preferred.
Minimum of 7 years of experience in semiconductor technology roles. Preferably, packaging integration, advanced packaging research, heterogeneous integration, process integration, package development, or related semiconductor process
Job Type
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location
US, Arizona, Phoenix
Additional Locations
US, Oregon, Portland
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
- Work Model for this Role
- This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
