Apply expertise in power integrity design and tradeoffs to guide simulations of power networks and physical implementations for packages and platforms.
Ensure on-die power noise meets system-on-chip (SoC) functionality and performance requirements.
Collaborate with silicon integration, die floor planning, and package design teams to optimize on-die decoupling partitions and implement package decoupling schemes.
Develop and deliver platform-level power shapes and decoupling solutions as part of platform design guides for customers.
Derive platform-level specifications from silicon specifications and drive convergence on feature sets, form factors, and voltage regulator performance
Qualifications
Minimum Qualifications
Minimum qualifications are required to be initially considered for this position.
Candidate must possess a bachelor's degree or higher in Electrical or Electronic Engineering.
Minimum of 5 years of experience on Technical Knowledge as electrical design engineer: Silicon, package or board level design.
Expertise in electrical characterization tools and methodologies.
Knowledge of power integrity design, power delivery networks, and hardware architecture fundamentals.
Expertise to perform power and performance analysis and optimization.
Familiarity with package fundamentals and voltage regulation principles.
Advanced English communication skills (written and oral).
Must have unrestricted - permanent right to work in Costa Rica.
Preferred Qualifications
Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Strong collaboration and communication skills, with a proven ability to work across teams to solve complex technical challenges.
Experience in disciplined execution to deliver results under tight schedules and competing priorities.
Electrical simulation software knowledge such as Sigrity PowerSI, PowerDC, HSpice, Matlab, HFSS
Proven ability to align technical solutions with broader business goals and customer needs.
Take the next step in your career and apply today to join Intel's talented team of engineers, shaping the future of power integrity solutions and driving innovation across the industry.
Job Type
Experienced Hire
Shift
Shift 1 (Costa Rica)
Primary Location
Costa Rica, San Jose
Additional Locations
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
- Work Model for this Role
- This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
