Maintain documentation of a hardware design specification, Pass design check list prior to tape out, BOM specifications and work with NPI team to build PCBA.
Lead design reviews and present design summary to management, highlight risks with mitigation plans.
Interface and work collaboratively with mechanical engineers, optical engineers, Photonics engineer, firmware engineers, process engineers and test engineers.
Design and coordinate with PI/SI engineers to simulate high-speed interfaces, RF traces, dc and ac PI analysis, etc. 100Gbps, 200Gbps NRZ and PAM4 signaling.
Interact with program manager, buyer/planner and suppliers to make sure designed parts are available in a timely manner for build.
Troubleshooting and performance optimization of the sub-system/transceiver module board.
Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.
Required Skills
Bachelor’s degree & 4+ years of experience or Master's degree & 3+ years of experience or PhD & 0 years in Electrical Engineering or similar STEM field.
3+ years of experience in the following
HW/circuit design, Schematic design and Layout floor planning.
Experienced in Cadence tools for schematic and layout.
High density and high-speed multiple-layer board design.
Voltage regulator, uController, DAC/ADCs component selection, design and layout optimization to meet product requirements.
PCB and product bring up, laboratory optical and electrical measurement skills.
High speed Tline design and layout guidelines (25-50G NRZ, 100Gbps PAM4 and above)
Preferred Skills
Experience working with high volume PCB/substrate fab houses. Selecting PCB stackup that meets product requirement.
Experience with electronics CAD tools and modeling. Experience in PI and SI simulations is a plus.
Knowledge of transceiver/test board electrical design principles, including module architecture, high speed signal integrity, crosstalk, power integrity, noise, soft start, ESD, FW, testing, etc.
Experienced in layout and able to direct layout engineer with clear design priority.
Understand principles of micro-controller and communication protocols such as SPI, I2C, MDIO, CMIS management interface for optical modules.
Experience working with AWG, DCAM, VNA/LCA to characterize high speed performance.
Strong communication and presentation skills.
Job Type
College Grad
Shift
Shift 1 (United States of America)
Primary Location
US, California, Santa Clara
Additional Locations
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
- Work Model for this Role
- This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
