Key Responsibilities
Develop and execute scalable IP verification plans, test benches, and methodologies to meet graphics microarchitecture specifications.
Perform debugging, issue replication, root cause analysis, and corrective measures in pre-silicon environments.
Conduct system simulations and analyze power, timing, and functional coverage to uncover and resolve design issues.
Independently create test environments, verify features, and ensure comprehensive coverage closure.
Collaborate with architects, design, and physical engineering teams to optimize functionality, performance, and power goals.
Utilize assertion-based verification techniques and industry-standard tools to improve verification reliability.
Document test plans and lead technical reviews to ensure alignment with architecture goals.
Maintain and improve functional verification infrastructure and methodologies for continuous enhancement.
Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.
Minimum Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field, plus 4+ years of relevant experience; OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field, plus 3+ years of relevant experience; OR
PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field with no prior professional experience in:
System Verilog, UVM, and object-oriented programming.
Developing feature verification test benches and achieving functional coverage closure.
Python or similar scripting languages.
Knowledge of assertion-based verification methodologies.
Preferred Qualifications
Exposure to GPU architecture fundamentals and computer architecture principles.
Debug experience with industry-standard frontend design and verification tools and flows.
Experience working with IP development teams and validation protocols (e.g., CXL, AXI, PCIe).
Strong teamwork and communication skills with a commitment to continuous learning.
Join Intel and play a pivotal role in shaping the future of graphics technology. Collaborate with world-class engineering teams to deliver innovative solutions that power tomorrow's computing revolution.
Job Type
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location
US, California, Folsom
Additional Locations
US, California, Santa Clara
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-200,340.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
- Work Model for this Role
- This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
