Performing analysis of either synthesis, place and route, floor planning or signoff for static timing analysis on timing paths, formal equivalence verification, power consumption, electrical rule checking, and circuit reliability to identify key issues.
Working closely with design teams to understand and debug tool issues and constraints.
Working with industry EDA vendors to build and enhance tool capabilities to design a high-speed, low-power synthesizable CPU.
Creating documentation and helping with guidelines/specs.
Communicating with other team members to solve problems and following solutions through to completion. Excellent verbal and written English communication skills.
Leverage AI capabilities to enhance daily operational efficiency and design productivity.
Qualifications
Minimum Qualifications
Bachelor's Degree in Computer Engineering and/or Electrical/Electronic Engineering and 1+ years of relevant working experience OR Master's Degree in Computer Engineering and/or Electrical/Electronic Engineering
Fresh Graduate is welcome to apply.
Preferred Qualifications
1+ years of experience in VLSI, design automation algorithms, and transistor-level design.
1+ years of experience using industry standard Engineering Design Automation (EDA) VLSI tools/flows from vendors such as Synopsys, Cadence and/or Mentor Graphics for performing synthesis, place-and-route, extraction, timing/power analysis and functional verification.
1+ years' experience with Python, Perl, and/or Tcl scripting languages.
1+ years of relevant working experience in microprocessor or other high speed design backend design.
Experience with timing closure methodology for worst-case corner (static timing analysis / STA, statistical variation analysis, spice circuit simulation, ERC, noise analysis flows, cross talk, OCV effects, budget constraints)
Job Type
Experienced Hire
Shift
Shift 1 (Malaysia)
Primary Location
Malaysia, Penang
Additional Locations
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
- Work Model for this Role
- This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
