Job Details
Job Description
The Role and Impact Join a Team That Defines the Heartbeat of Next-Generation CPUs. As a CPU Senior Clock Design Engineer, you will contribute to the design, implementation, analysis, and optimization of clock distribution networks that enable industry-leading performance, power efficiency, and product scalability.
Business group You will be part of Intel Corporation, joining a dynamic team dedicated to designing high-performance CPUs that drive Intel's leadership in the semiconductor industry. This group focuses on delivering cutting-edge solutions that support Intel's mission of creating world-changing technologies to enrich lives. Collaborating across multiple domains, the team enables groundbreaking designs that align with Intel's broader goals of innovation and excellence.
Key Responsibilities
- Design, implement, and optimize clock distribution networks for high-performance CPU and SoC products.
- Contribute to clock architecture development and clock tree synthesis (CTS) methodologies.
- Perform timing analysis and support timing closure across complex semiconductor designs.
- Develop custom circuits, library cells, and clock-related design solutions.
- Analyze performance, power, area, and timing tradeoffs to improve product efficiency.
- Create automation solutions using scripting and programming languages to improve design productivity.
- Collaborate closely with architecture, design, physical implementation, validation, and EDA teams.
- Support debug, validation, and optimization activities throughout the product development lifecycle.
- Drive technical issues to closure while maintaining high-quality engineering standards.
- Influence future methodologies, design flows, and clocking technologies.
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Qualifications
- Minimum Qualifications
- Bachelor's degree in Electrical, Electronics, or relevant field and 3+ years of hands-on experience in physical design implementation OR Master's degree in Electrical, Electronics, or relevant field with 2+ years of experience.
- Extensive experience in clock tree synthesis (CTS) techniques and methodologies using Synopsys and Cadence platforms.
- Strong understanding of submicron process node technologies and layout verification methods such as LVS/DRC.
Preferred Qualifications
- Strong ownership and accountability for technical deliverables.
- Curiosity and passion for solving complex engineering challenges.
- Effective problem-solving and analytical thinking skills.
- Ability to collaborate across multiple engineering disciplines.
- Strong communication skills with both technical and non-technical stakeholders.
- Adaptability and willingness to learn new tools, technologies, and methodologies.
- Ability to balance multiple priorities in a fast-paced environment.
