Define and analyze CPU power and performance requirements, budgets, and interfaces within the SoC, working across CPU cores, shared caches, interconnects, memory, accelerators, and platform IP.
Create and maintain workload-based CPU and SoC power and performance models and targets; correlate predictions with pre- and post-silicon data; and apply the results to improve current implementations and future architectures across idle, sustained, burst, and peak workloads.
Partner with firmware and operating system teams to define end-to-end CPU and platform power-management capabilities, including DVFS policies, clock and power gating, idle-state management, telemetry, residency, latency, and quality-of-service tradeoffs.
Influence CPU microarchitecture and SoC fabric, memory, and I/O architecture to optimize power efficiency, performance, throughput, latency, and quality of service under representative real-world workloads.
Lead cross-functional architecture and design reviews, drive tradeoff decisions across power, performance, area, cost, thermals, and product experience, and align CPU, SoC integration, validation, firmware, operating system, and product teams.
Translate product usage models and competitive insights into clear architectural requirements, feature specifications, and measurable success criteria; track execution and communicate risks, decisions, and progress to technical and product leadership.
A successful candidate will also demonstrate
System-level thinking and the ability to connect detailed design decisions to CPU, SoC, and product-level outcomes.
Strong analytical problem-solving skills, with an emphasis on innovation, feasibility assessment, and disciplined exploration of architectural tradeoffs.
Technical leadership and communication skills to influence CPU architecture, SoC design, firmware, validation, and product roadmaps across organizational boundaries.
Curiosity, initiative, and a willingness to expand deep technical expertise into broader architecture ownership while advancing energy-efficient computing.
Qualifications
The minimum qualifications below are required for consideration. Preferred qualifications are additional attributes that may help candidates succeed in the role. Relevant experience may be gained through architecture, design, modeling, validation, firmware, or other closely related engineering roles.
What We Need to See (Minimum Qualifications)
Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field with 6+ years of relevant experience; master’s degree with 4+ years; or PhD with 2+ years. The specialized experience described below may be included within this overall experience.
Within that experience, 4+ years in SoC or IP architecture, CPU or SoC design, microarchitecture, power and performance engineering, or a closely related technical field.
How to Stand Out (Preferred Qualifications)
Extensive experience in CPU or SoC design, microarchitecture, architecture, or power and performance engineering; candidates with deep design expertise and demonstrated system-level leadership who are ready to grow into an architecture role are encouraged to apply.
Proven experience designing, integrating, or architecting compute SoCs, CPUs, or complex silicon IP, with an understanding of how local design decisions affect system-level power, performance, and product behavior.
Knowledge of CPU or SoC power-management concepts such as DVFS, clock and power gating, idle states, telemetry, thermal constraints, or firmware and operating system interactions; direct ownership in all areas is not required.
Advanced knowledge of computer architecture, CPU microarchitecture, system-level design, and the interactions among cores, caches, interconnects, memory, accelerators, and platform IP.
Experience with performance or power modeling, benchmarking, workload analysis, functional modeling, statistical analysis, or correlation of model predictions with silicon measurements.
Demonstrated ability to lead technical tradeoffs, communicate across design, architecture, firmware, validation, and product teams, and expand from detailed design ownership to broader architectural decision-making.
Bring your technical depth, system-level perspective, and passion for energy-efficient computing to Intel. Join us in developing CPU power-management innovations that shape the performance, efficiency, and user experience of future client products.
Benefits at Intel
Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion.
Job Type
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location
US, California, Folsom
Additional Locations
US, California, Santa Clara
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $164,470.00-311,890.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
- Work Model for this Role
- This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
