Qualifications
Minimum Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with 12+ years of experience in RTL design for ASIC/SoC development; OR Master's degree in relevant field with 8+ years of experience; OR PhD in relevant field with 6+ years of experience. Advanced proficiency in RTL design using Verilog/SystemVerilog and hands-on experience in SoC system integration. Expertise in standard bus protocols (AXI, AHB) and embedded processor architectures. Demonstrated ability to address design challenges, including clock domain crossings, power optimization, and timing closure. Proficiency in scripting languages (e.g., Python, TCL) for automation and design flow customization.
Preferred Qualifications
- Strong knowledge of high-speed and low-power design techniques.
- Familiarity with industry-standard EDA tools such as HDL simulators (VCS, Questa, IES), lint tools (Spyglass), and FPGA prototyping tools (Xilinx Vivado, Altera Quartus II).
- Experience in SoC multicore CPU subsystem design and GPU cache development.
- Collaborative mindset and leadership skills, with a passion for innovation and solving complex technical challenges.
Join us to shape the next generation of AI hardware and make an impact on tomorrow's technological advancements.
Job Type
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location
US, California, Santa Clara
Additional Locations
US, California, Folsom, US, Oregon, Hillsboro, US, Texas, Austin
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
