Responsibilities include, but are not limited to
Characterize and model the impact of advanced 3D integration technologies, including TSVs, hybrid bonding, wafer thinning, and backside processing, on device performance metrics such as mobility, threshold voltage (Vt), leakage, matching, and variability.
Evaluate stress, thermal, and electrical coupling effects, including keep-out zone (KOZ) behavior and device interactions within complex 3D stacks.
Define and develop device and passive test structures to study 3DIC effects, including TSV proximity, KOZ, guard ring, resistor, and capacitor structures.
Drive electrical test (e-test) strategy, data collection, and silicon analysis to accelerate technology learning and optimization.
Provide device characterization inputs that enable design rule development, compact models, PDKs, and 3D design kit releases in collaboration with Design Enablement teams.
Partner closely with Process Integration, Packaging, Assembly, Reliability, Yield, and Program Management organizations to identify, troubleshoot, and resolve device-related issues.
Evaluate customer requirements for analog, mixed-signal, RF, and high-speed I/O devices within 3D architectures, assessing technical feasibility, risk, and implementation timelines.
Support technology qualification and manufacturing readiness activities, including device targeting, monitoring strategies, yield improvement efforts, and excursion management.
Communicate complex technical findings and recommendations to engineering, business, and customer stakeholders.
What We Are Looking For
The successful candidate will demonstrate
Deep understanding of CMOS device physics and the impact of process, stress, and thermal effects on device performance.
Strong analytical and problem-solving skills, including data science, statistical analysis, and scripting capabilities.
Excellent written and verbal communication skills with the ability to explain complex technical concepts to diverse audiences.
Proven ability to influence and collaborate across device, process, packaging, manufacturing, and design organizations.
Strong ownership mindset, technical curiosity, and a passion for developing innovative solutions in advanced semiconductor technologies.
Qualifications
The Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
Master's degree in Electrical Engineering, Physics, Materials Science, or a related field with 4+ years of industry experience, in semiconductor device engineering, process integration, advanced packaging, or related technology development.
3+ years of experience in advanced CMOS device characterization and electrical parametric (e-test) data analysis.
Hands-on experience with one or more advanced packaging and 3D integration technologies, including:
Through-silicon vias (TSVs)
Hybrid bonding
Wafer-to-wafer or die-to-wafer bonding
Micro-bump technologies
Wafer thinning
Backside power delivery
Preferred Qualifications
PhD in Electrical Engineering, Physics, Materials Science, or a related field.
Experience analyzing stress and thermal interactions affecting device behavior, including TSV keep-out zones and chip-package interaction effects.
Expertise in test structure development, design of experiments (DOE), and e-test program implementation.
Knowledge of device modeling, design rule development, PDK generation, or design technology co-optimization (DTCO).
Experience using TCAD and/or finite element analysis tools for stress, thermal, or device simulations.
Understanding of semiconductor reliability mechanisms, including electromigration (EM), time-dependent dielectric breakdown (TDDB), bias temperature instability (BTI), and bonding interface reliability.
Experience with advanced node technologies, including FinFET and Gate-All-Around (GAA) devices.
Semiconductor foundry experience with direct customer engagement and technical support.
Experience supporting technology transfer and production ramp in high-volume manufacturing environments.
Join us in shaping the future of semiconductor innovation through advanced 3D integration technologies that enable the next generation of AI, HPC, and memory solutions.
Job Type
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location
US, Oregon, Hillsboro
Additional Locations
US, Arizona, Phoenix, US, California, Santa Clara
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $136,900.00-269,150.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
- Work Model for this Role
- This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
