#WeAreIn to create tiny chips and big careers.
The future won’t wait... why should you? Join us and make a difference. Whether you join as a student, intern, or trainee, you'll be part of something real - real projects, real impact, and real opportunities to grow.
Are you in?
Your role
Key responsibilities in your new role
- As our Digital
- Functional Verification Working Student, you
- will support our verification team in exploring and applying cutting-edge
- verification technologies, while gaining hands-on experience in real project
- work at the intersection of digital design and AI-driven innovation.
Experience
- research: Research and
- evaluate state-of-the-art verification concepts including SystemVerilog UVM,
- functional verification, and formal verification
Experience project work: Support
- verification and automation tasks within ongoing projects and help drive topics
- to completion
- Focus on the future: Explore AI-based
- methods and applications for functional and formal verification in a practical
- project environment
- Shape the future: Conduct research
- on how AI can improve verification efficiency, coverage, and analysis
- Teamwork Is Dreamwork: Work closely
- with experienced verification engineers and contribute to real project work
- Your profile
- Qualifications and skills to help you succeed
Study Field: Currently enrolled in a technical degree program (e.g., electrical engineering, computer engineering, or computer science)
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Way of working
Strong problem-solving skills, with the ability to analyze complex technical issues and develop creative solutions
Collaborative team player with a proactive attitude who enjoys working closely with experienced engineers
Structured approach to work with strong organizational skills
Solid foundation in object-oriented programming and familiarity with Python and scripting languages
Good knowledge of digital circuit design principles, along with practical experience in Verilog and SystemVerilog and strong debugging skills
Familiarity with EDA tools (simulators, waveform debug, lint, formal) is a plus
- Nice-to-Have
- Skills: Prior knowledge of SoC verification processes, especially SystemVerilog UVM, is highly preferred
Language skills: Good written and spoken English skills
- Please attach the following documents to your
- application:
CV in English
Certificate of enrollment at university
Latest grades transcript (not older than 6 months)
High school report
Important information
- Working part-time: The focus is on
